Abstract: A delay generator having very high accuracy and stability over temperature variations and time, suited for very short delay times, such as in clock recovery circuits in very high-speed digital data transmission systems. A delay line, having one end either open or shorted and a round-trip delay time of .tau., is driven by a voltage source, the output impedance thereof matched to the delay line, and a current source. The current source and the voltage source are driven by an input signal to be delayed. The voltage source is provided by a transistor operating as a voltage follower, which also operates to provide as an output a signal dependent on the difference between the input signal and the voltage on the delay line. This output serves as the output of the delay generator, the input signal delayed by a the time .tau..

Abstract: A fully differential variable delay element for providing precision delays for use in digital phase-locked loops or the like. The delay in each stage is controlled by changing bias currents and the coupling of a capacitance load thereto, therby reducing the sensitivity of the delay element to electrical noise at low bias current levels (long delay times). Included is a circuit which substantially removes any skew in the differentially delayed signals from the delay element.

Abstract: An operational amplifier and method for making same, with predetermined common mode voltage gain, adapted to form an amplifier and a voltage regulator. The predetermined common mode voltage gain allows for substantially reduced differential mode gain and wider operating bandwidth with little distortion, compared to amplifiers and voltage regulators using operational amplifiers of the prior art. Further, examples of operational amplifiers, having the reduced differential mode gain and predetermined common mode gain, are given for implementation in CMOS and bipolar technologies.

Abstract: A method of removing natural oxides and other contaminants on silicon or polysilicon and then depositing polysilicon thereon. The natural oxide is substantially removed from the exposed silicon with an anhydrous etchant and then the polysilicon is deposited on the exposed silicon. The etching and depositing steps occur in the same reactor chamber (in-situ). A portion of the end of the selective etching step overlaps with a portion of the beginning of the polysilicon deposition step to achieve an interface between the underlying silicon and the deposited polysilicon that is substantially free of native oxides and other contaminants.

Abstract: This invention relates to a method of allocating new telecommunications cells to one of a plurality of processors, and to control acceptance of new calls when in overload. The method is based on measuring the real time occupancy of each processor periodically, and allocating new calls for the following period in such a way as to attempt to make each processor's occupancy approach the average occupancy of all the processors. An overload state is detected when the average occupancy of the processors in one period exceeds a predetermined threshold, e.g., 90%. When this happens, load is shed in an amount calculated to restore the average occupancy to the threshold value over a number of periods of time. Advantageously, this method optimizes the call processing capacity of the processors.

Abstract: A voltage variable capacitor (VVC) having two terminals in a variable frequency crystal oscillator integrated into a common substrate with the oscillator circuitry and isolated therefrom. The VVC is constructed using the same processing steps as the oscillator circuitry and achieves low series resistance and wide capacitance variation by utilizing a substrate or epitaxial layer (body) having a well with a diffused region therein. The region, of the same conductivity type as the well and a first one of the two terminals, forms a rectangular ring in the well. Over the region and insulated therefrom, a conductive layer is deposited to provide a second one of the two terminals. Both terminals are electrically isolated from the body.

Abstract: A method for selectively etching higher aluminum concentration AlGaAs in the presence of lower aluminum concentration AlGaAs or GaAs, preferably at room temperature. The AlGaAs is first cleaned with a solution of NH.sub.4 OH and rinsed. The AlGaAs is then etched in a solution of HF. If photoresist is used on the AlGaAs, the photoresist may first be baked to increase the adhesion of the photoresist to the AlGaAs and to "toughen" the photoresist to reduce undercutting thereof. Agitation is applied to the AlGaAs or the etchant to assist in the uniform etching of the AlGaAs.

Abstract: A novel logic gate, using Gallium-Arsenide technology, that is compatible with TTL or CMOS logic. This logic gate operates off a single voltage supply (e.g. 5 volts) and implements complex logic functions within a single logic gate, such as "AND-OR-INVERT". This is accomplished by having at least one FET with the gate terminal coupling to a current limiter, a first source/drain terminal coupling to the input of a logic sub-circuit, such as a DCFL circuit, and a second source/drain terminal coupling to the input of the logic gate. A diode disposed between the first source/drain terminal and the input to the logic sub-circuit sets the switching voltage of the logic gate. Parallel-connected FETs performs the logical "AND" sub-function while the logic sub-circuit performs the logical "OR" and "INVERT" sub-functions. Also disclosed is a buffer circuit for driving large loads while providing large output voltage swings.

Abstract: An optically bistable device, such as a symmetric self electro-optic effect device (S-SEED), is forced into a metastable state prior to the incidence of an optical input signal thereto, thereby increasing the sensitivity of the optically bistable device to the optical input signal, reducing both the switching time and the optical input signal energy required to switch the device. The metastable state is entered into by one of three techniques: (1) turning off the bias voltage V.sub.0 of the device with optical bias beams on then turning on the bias voltage V.sub.0 with the optical bias beams off; (2) applying a predetermined voltage to a node in the device, the predetermined voltage being substantially the metastable state voltage or V.sub.0 /2; or (3) subjecting the device to equal intensity optical bias beams having a wavelength longer than the exciton wavelength.

Abstract: A circuit is disclosed which converts CMOS logic input signals to ECL output signals. A pair of FETs, arranged as a conventional CMOS inverter, responds to the CMOS logic input signals and drives a bipolar transistor operating as a voltage follower. The emitter of the bipolar transistor serves as the output of the buffer providing the ECL output signals. A resistor having a predetermined resistance couples between a voltage source and the base of the bipolar transistor. First one of the pair of FETs couples a constant current source to the resistor and the base of the bipolar transistor when the buffer is supplying an ECL logical "zero" logic signal. The current from the current source passing through the resistor establishes the ECL logical "zero" output voltage. Second one of the pair of FETs shunts the resistor when the buffer is supplying an ECL logical "one" output, allowing faster transitioning of the output of the buffer from an ECL logical "zero" to a logical "one".

Abstract: A novel analog comparator having cascaded gain stages powered by two buses, the voltages on which are dependent on a reference input voltage. A network, responsive to the reference input voltage, sets the voltages on the buses and isolates the buses from external power and ground to achieve high power supply and ground noise immunity. An alternative design of the network is provided which removes errors in the accuracy of the comparator resulting from differing drain-to-source voltages across the various transistors. The accuracy of the comparator is then dependent on the accuracy of matching predetermined ratios of the sizes of the transistors.

Abstract: A combined binary and binary coded decimal (BCD) arithmetic logic unit (binary/BCD ALU) having a binary adder adapted to perform decimal operations on BCD data without impacting the performance of binary operations. The combined binary/BCD ALU has a look-ahead carry binary adder for generating the binary sum or logical combination of inputs to the binary adder to an output (Y), the Y output being arranged in groups of four bits. The binary adder additionally provides carry outputs Co.sub.i of the binary additions from each of the groups of four bits of the Y output. A decimal correction unit, responsive to the Y and Co.sub.i outputs from the binary adder [ALU means], corrects the binary sum from the binary adder when performing BCD arithmetic. A multiplexer selects the Y output from the binary adder to a result output when performing operations on binary data. Alternately, the multiplexer selects the output from the decimal correction unit to the result output performing operations on BCD data.

Abstract: An improved CMOS bandgap voltage reference in which a magnified current derived from a thermal voltage reference produces a voltage drop across a resistor. The resistor in turn couples to a single bipolar transistor which is part of the thermal voltage reference. The bandgap voltage is the sum of the voltage across the resistor and the voltage across the bipolar transistor. In addition, the immunity of a bandgap voltage reference to variations in power supply variations is improved by having a differential amplifier sense the voltages at the control current input and the output of a current mirror in the thermal voltage reference portion of the bandgap voltage reference and adjusting the power supply voltage to the thermal voltage reference until the sensed voltages are substantially the same.

Abstract: A novel fully differential analog comparator having cascaded gain stages powered by two buses. The two buses are powered by a current source and a variable gain current mirror responsive to the current source. The current source and the current mirror isolate the buses from external power and ground to achieve high power supply noise immunity. True and complementary outputs of the comparator are provided having an adjustable output common mode voltage to optimize the driving of subsequent logic gates responsive to the comparator.

Abstract: A groove is disposed in a substrate longitudinally along the outside radius of a bent integrated optical waveguide to constrain the mode of optical energy propagating therein such that the optical energy that would normally be radiated is confined to the waveguide, thereby reducing transmission loss through the bend. Further, to reduce coupling loss between an integrated optical waveguide and an optical fiber, two grooves are disposed longitudinally along either side of the integrated optical waveguide to constrain the mode of optical energy propagating in the waveguide to approximate the mode of the optical energy propagating in the optical fiber. To further reduce both bend and coupling losses, the ends of the grooves bend away from the waveguide.

Abstract: A TTL to CMOS static input buffer, and method for making same, having a first transistor (32) of a first conductivity type, having a control terminal responsive to a TTL input signal, a first output terminal coupled to a first voltage supply (Vdd) and a second output terminal; a second transistor (31) of a second conductivity type, having a predetermined threshold voltage, a predetermined width-to-length ratio, a control terminal responsive to the TTL input signal, a first output terminal coupled to an output node and a second output terminal coupled to a second voltage supply; a third transistor (33) of the second conductivity type, having a predetermined threshold voltage, a predetermined width-to-length ratio, a control terminal coupled to an intermediate voltage source, a first output terminal coupled to the second terminal of the first transistor and a second output terminal coupled to the output node; and a CMOS inverter (35) having a predetermined threshold voltage Vb; wherein the static input buffer h

Abstract: Parallel elongated trenches in a silicon substrate are utilized to form multiple distinct memory cell capacitors on each continuous wall of each trench. Chanstops are formed between adjacent capacitors to achieve electrical isolation. A separate word line overlies each trench wall and is connected via respective MOS transistors to the spaced-apart capacitors formed on the wall. A reliable high-density memory characterized by excellent performance is thereby realized.

Abstract: An improved differential input amplifier stage used as the input stage in digital differential line receives or operational amplifiers. The differential input amplifier stage has a pair of input transistors forming a differential pair with a common output node and two complementary output nodes; a current mirror, coupled to the two complementary output nodes and responsive to a first one of the two complementary output nodes and a single-ended output signal on the second one of the two complementary output nodes; and a current source transistor coupled to the common output node and responsive to the first one of the two complementary output nodes. The current source transistor maintains the voltage on the first one of the two complementary output nodes substantially constant, thereby improving common mode and power supply noise immunity and providing faster differential response by the differential input amplifier stage.

Abstract: A folded bit line configured DRAM, with standard even and odd rows of memory cells, also includes spare even and odd rows of memory cells which can be substituted for standard rows found to have defective cells or interconnections. Each of the decoders associated with a standard row includes provision for being disconnected if found to be associated with a defective row. One common spare decoder is associated with one spare even and one spare odd row of memory cells. Each spare decoder is designed normally to be deselected for any address but to be able to assume the address of any disconnected standard row. Disconnection of a standard decoder and substitution of a spare decoder with the appropriate even or odd row are made possible by appropriate inclusion of fusible links which are selectively opened by laser irradiation. The use of one spare decoder with both an even and odd row serves to reduce the number of needed spare decoders and thus reduces overall chip size.

Abstract: A technique for providing high current carrying metal conductors for coupling to transistors or the like to increase the current carrying capacity of the transistor without substantial increase in size. The conductors are tapered along the axis of current flow with current being conducted to or from the tapered portion of the conductors, such that the current density therein is substantially constant.