Abstract: Briefly, in accordance with the embodiment of the invention, a refined timing recovery circuit for retiming a colored data signal comprises a data pulse edge detector. The recovered data signal is derived from a received data pulse. The data pulse edge detector is adapted to be coupled to an oversampling clock. The data pulse edge detector is further adapted to sense the next clock pulse edge having the closest temporal proximity after a selected received data pulse edge. In accordance with another embodiment, an integrated circuit comprises: a timing recovery system for retiming a recovered data signal derived from a received data pulse, the timing recovery system comprising a refined timing recovery circuit. The refined timing recovery circuit includes a data pulse edge detector.

Abstract: An improved sample and hold circuit utilizing a buffer circuit to reduce the effective resistance of the switches used to couple an input signal to storage capacitors. The effective resistance of the switches are reduced by placing the switches within the feedback path of the buffer. The buffer may be shared among multiple sample and hold circuits.

Abstract: A telephone line-powered Data Access Arrangement having amplifiers therein directly powered from the telephone line without voltage regulators or filters. The amplifiers, such as the amplifier driving an LED in an optical isolator, draw a constant power supply current independent of the signal being amplified. Thus, amplified signals are not coupled back onto the telephone line.

Abstract: An electronic hybrid useful in telephone line-powered Data Access Arrangements. The hybrid has a transmit amplifier with an output driving the base of a bipolar transistor. The emitter of the transistor is connected to a sense resistor which is, in turn, connected to one wire of a telephone line. The collector of the transistor connects to another wire of the telephone line. A summing node couples together signals on the telephone line and signals across the sense resistor such that the remaining signal on the summing node is substantially the signal received from the telephone line without the signal to be transmitted.

Abstract: An energy efficient logic gate circuit design that provides a substantially constant load to a clock source regardless of logic signal inputs to, or outputs from, the gate. The gate provides two complementary outputs and utilizes cross-coupled transistors to ensure that the outputs remain valid (complementary) after the logic inputs become invalid. Two blocks, each having a node coupling to the clock source and performing complementary logic functions, in combination with diodes for recharging the outputs of the gate, present the constant load to the clock source.

Abstract: A transformer-less electronic ballast for a gas-discharge lighting system having a power amplifier, with an input, driving a gas-discharge lamp in combination with reactive elements to form a resonant load. The lighting system includes a resistor for sensing current flowing in the resonant load, a comparator having an output coupled to the input of the power amplifier, a non-inverting input coupled to the resistor, and an inverting input coupled to the output of a ramp generator, polarity of the ramp signal being dependent on the output of the comparator. The comparator generates a first signal that is amplified by the power amplifier and applied to the load. The ramp generator generates a ramp signal in response to the first signal. The first signal is asserted by the comparator when the sensed current flowing in the load differs from the ramp signal.

Abstract: A method of making a gettering structure for dielectrically isolated wafer structures, such as bonded wafers. A getterer layer is deposited over the wafer having semiconductor regions isolated from each other by trenches. The polysilicon is etched back leaving the polysilicon on the sides of the regions. The polysilicon may be doped. The polysilicon is oxidized and a second layer of polysilicon may be deposited to fill voids in the trenches.

Abstract: A master-slave differential comparator having a threshold value. The master section controls the threshold value of the slave section. The slave section is controlled by bias currents therein to matching same in the master section. The bias currents are substantially determined by fixed biases applied to the master section, the difference in biases being substantially equal to the threshold value of the comparator.

Abstract: A mixture of buffered hydrofluoric acid (e.g., HF and NH.sub.4 F) and a treating agent (e.g., acetic acid, phosphoric acid, hydrochloric acid, sulfuric acid or formic acid) is used to produce a matte finish on the pure silica cladding of an optical fiber. The matte finish may be used to increase the adhesion of other materials to the glass (e.g., of metal coatings to silica fibers) or to reduce glare.

Abstract: An amplitude control scheme for a high bit rate digital optical transmitter is disclosed. The data to be transmitted by the laser is pulse-width modulated by a low frequency signal. The pulse-width modulated signal is applied to the laser via a laser driver and to a mark density reference generator. The magnitude of the low frequency components from the mark density reference generator is a signal indicative of the desired amplitude of the laser light pulses. A back-face photodiode converts a portion of the laser light into an electrical signal, the magnitude of the low frequency portion thereof being a signal indicative of the actual amplitude of the laser light pulses. The actual amplitude of the laser light pulses is compared to the desired amplitude and the laser driver output amplitude may then adjusted to compensate for variations in the laser performance.

Abstract: A variable delay line having a string of "slow" logic inverters and an equal number of "fast" inverters with inputs connected to corresponding "slow" inverter inputs. Transmission gates, coupling the "fast" inverter outputs to corresponding "slow" inverter outputs, vary the amount of current from the "fast" inverters added to the output current of the corresponding "slow" inverters. Maximum delay occurs when substantially no current from the "fast" inverter is added to the "slow" inverter output current and minimum delay occurs when substantially all the current from the "fast" inverter is added to the "slow" inverter output current. The variable delay line may be configured into a variable frequency ring oscillator, useful in phase-locked-loops or the like.

Abstract: A gas-discharge lighting system having an inductor and at least two capacitors in combination with a gas discharge lamp, the inductor and capacitors forming a resonant system, the resonant frequency thereof being dependent upon whether the lamp is nonionized or ionized. The lamp is operated by driving the lamp, inductor, and capacitor combination with a signal of a first polarity and inverting the polarity when the signal current transitions a predetermined current level. This repeated until the polarity of the signal remains of one polarity longer than a predetermined time, at which time the signal is inverted. This is repeated indefinitely. The predetermined length of time is one-half the inverse of a minimum frequency greater than the ionized resonant frequency.

Abstract: Two methods are disclosed for providing a warm-up or pre-heat period for a gas-discharge lighting system, such as a fluorescent light. One method provides current to the lamp for a predetermined period of time to heat the filaments therein without significant ionization of the lamp. The second method provides current to the lamp to heat the filaments without significant ionization of the lamp until the voltage across the filament reaches a predetermined voltage. After the lamp is pre-heated, the current is increased to ionize the lamp.

Abstract: A current reference using a switched capacitor to produce a substantially temperature invariant output current. Charge subtracted from a relatively large capacitor by a much smaller switched capacitor at a chosen rate substantially determines the output current of the reference. The output current is proportional to the product of a reference voltage, the capacitance of the switched capacitor and the switching frequency.

Abstract: A method of detecting whether a valid DS1 signal is being received by a receiver. If the receiver does not have a valid signal (loss of signal), then the receiver reads consecutive fixed sized N bit blocks of the received digital signal. Each of the blocks or windows is checked for minimum 1s density. Received consecutive 0s are counted and checked against a maximum. If two sequential blocks of bits satisfy the 1s and consecutive 0s tests, then the received signal is judged valid and an acquisition of signal flag is asserted.

Abstract: A method of making a doubly-diffused MOS (DMOS) device that can tolerate higher drain dV/dt before latch-up occurs. At least some of the immediately adjacent multiple body regions in the DMOS device are interconnected at the corners thereof by the formation of P-conductivity regions. These regions reduce parasitic bipolar effects and facilitate collection of excess carriers in the device that causes latch-up under high dV/dt conditions and reduced avalanche energy tolerance.

Abstract: An amplitude control scheme for a high bit rate digital optical transmitter is disclosed. The data to be transmitted by the laser is pulse-width modulated by a low frequency signal. The pulse-width modulated signal is applied to the laser via a laser driver and to a mark density reference generator. The magnitude of the low frequency components from the mark density reference generator is a signal indicative of the desired amplitude of the laser light pulses. A back-face photodiode converts a portion of the laser light into an electrical signal, the magnitude of the low frequency portion thereof being a signal indicative of the actual amplitude of the laser light pulses. The actual amplitude of the laser light pulses is computed to the desired amplitude and the laser driver output amplitude may then adjusted to compensate for variations in the laser performance.

Abstract: A process for planarizing a bonded wafer. The wafer has a layer of exposed oxide thereon which acts as a reference for the grinding and polishing of the wafer. The resulting ground and polished wafer has a thinned, substantially planar, working layer for subsequent fabrication of transistors, etc.

Abstract: A fast turn-off circuit for solid-state relays or the like. The relay has a photodiode array for controlling the conductivity of an output transistor. A JFET switch closes to discharge the gate of the output transistor when a photodiode array stops producing current. A bipolar transistor switch, upon detecting the JFET switch closure, discharges the photodiode array.

Abstract: A delay-locked-loop (DLL) controls the cutoff frequency of a filter in an exemplary mass storage servo control channel. The cutoff frequency is adjusted in response to a clock pulse which updates the DLL. Between pulses, the DLL holds its value, reducing power consumption. The DLL has a fixed delay (precision) and a variable delay cell producing two delayed outputs, one output a predetermined amount after the other output. The DLL locks the delayed pulses from the variable delay cell to straddle a delayed pulse from the precision delay. The filter has selectable resistors and capacitors for adjusting the frequency thereof. Substantially identical selectable resistors and fixed capacitors are in the variable delay cell. The DLL selects which resistors in the variable delay cell (and corresponding resistors in the filter) results in the straddled delayed pulses. The capacitors in the filter are selected for the approximate desired cutoff frequency of the filter.