Abstract: A programmable integrated circuit (see FIG. 13) includes a plurality of routing resources including collinearly extending routing wire segments and a test circuit for testing the integrity of the routing wire segments. The routing resource structures include a plurality of unprogrammed antifuses disposed between routing wire segments and a plurality of transistors disposed electrically in parallel with a corresponding respective one of the antifuses. The test circuit has a common node that may be coupled to a selected one of the routing resource structures for testing. In test mode, the test circuit detects whether a current flows through the selected routing resource structure and in response provides either a digital low value or a digital high value on an output node.

Abstract: An automatic gain control (AGC) system for use in line locators that detect concealed conductors is presented. The AGC system includes determining an AGC signal from a reference sensor and processing signals from one or more observed sensors utilizing the AGC signal. The reference sensor is located farther from the concealed conductor than the observed sensors. The AGC system can be implemented in analog form or can include a digital AGC determination in a microprocessor.

Abstract: A stage assembly for precision movement in the x and y-directions, especially adapted for use in electron beam lithography for holding a reticle. The stage assembly includes a vacuum enclosure in which a magnet plate structure moves in the y-direction under the influence of a linear motor with respect to the enclosure. Riding inside the magnet plate is the stage which holds the reticle and moves in both the x and y-directions. x-direction movement is accomplished by the stage moving under the influence of "turnaround motors" in the x-direction. A turnaround motor at each end of the stage is only on for a brief period in order to drive the stage relative to the magnet plate in the x-direction. Then the other turnaround motor at the other end of the stage turns on and stops the movement of the stage in that direction and drives it back in the opposite direction. Reaction forces used to move the stage are transferred to the ground independent of the electron beam column supports.

Abstract: A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and a second level cache memory which includes a DRAM array coupled to the CPU bus. When accessing the DRAM array, row access and column decoding operations are performed in a self-timed asynchronous manner. Predetermined sequences of column select operations are then performed in a synchronous manner with respect to a clock signal. A widened data path is provided to the DRAM array, effectively increasing the data rate of the DRAM array. By operating the DRAM array at a higher data rate than the CPU bus, additional time is provided for precharging the DRAM array. As a result, the precharging of the DRAM array is transparent to the CPU bus. A structure and method control the refresh and internal operations of the DRAM array.

Abstract: A circuit for voltage translation includes protection against gate oxide breakdown when translating a lower voltage signal into a higher voltage signal. An input signal inverter circuit inverts the lower voltage signal into an intermediate signal having an increased minimum value. By raising the maximum value of the intermediate signal to the voltage level of the higher voltage signal, an output signal inverter circuit produces a driving signal to drive an output stage. However, because the increased minimum value of the signal is maintained, the gate oxide breakdown voltage is not exceeded in the circuit. The circuit also includes a blocking transistor between the input signal inverter and the output signal inverter to prevent the larger driving signal from overloading the input inverter circuit.

Abstract: A method for sensing a close to ground signal recieved from an array cell within a memory array includes the steps of providing a reference unit with a reference cell having a similar structure and a similar current path therethrough to that of the array cell, providing a timing unit with a timing cell having a similar structure and a similar current path therethrough to that of the array cell, discharging the array, the reference unit and the timing unit prior to charging them, generating a cell signal, a reference signal and a timing signal, respectively, upon charging, generating a read signal when the timing signal at least reaches a predefined voltage level and generating a sensing signal from the difference of the cell and reference signals once the read signal is generated. The reference unit has a reference capacitance which is a multiple of the expected capacitance of a bit line of the array and the timing unit has a predefined timing capacitance.

Abstract: An anode includes an anode cup, a membrane and ion source material, the anode cup and membrane forming an enclosure in which the ion source material is located. The anode cup includes a base section having a central aperture and the membrane also has a central aperture. A jet is passed through the central apertures of the base section of the anode cup and through the membrane allowing plating solution to be directed at the center of a wafer being electroplated.

Abstract: In a network switch, data received on an input connection can be transmitted on one or more output connections. When the switch receives a command to remove an output connection, the switch queues a marker cell in a queue cells to be transmitted on the output connection. The switch removes the connection when the switch reaches the marker cell as the switch traverses the queue to transmit the cells. A separate queue is provided for each input connection. For each input connection, the switch maintains a linked list of data structures each of which identifies an output connection which is to transmit data received on the input connection but for which the corresponding queue does not have data ready to be transmitted. When the queue gets data ready to be transmitted on all the output connections in the linked list, these output connections are moved to another linked list maintained for output connections for which there is a queue having data ready to be transmitted.

Abstract: A method of depositing a premetal dielectric layer involves deposition of a triple premetal dielectric layer in in-situ deposition in a single fabrication tool with each subsequent layer being deposited after a previous layer with no intervening handling step. Thus, no intervening cleaning steps or other intermediate steps are performed.

Abstract: A grid array assembly method and apparatus uses a flex circuitry substrate and includes providing a series of conforming flex circuitry substrates, the flex circuitry substrates include bonding pads and metallization on a first surface and, holes in the substrate which define a contact pad array on the opposite surface. The substrates are tested and acceptable, then mounted on a carrier strip with longitudinally aligned apertures. The carrier strip is typically a metal such as copper. The strip with mounted substrates is then passed to a station where an IC die is mounted on the substrate first surfaces wire bonds are placed from the die to the bonding pads, and the assembly is encapsulated by auto-molding to form a package body. Subsequently, interconnecting bumps are placed on the contact pads and the assembly is removed from the strip.

Abstract: A method of semiconductor fabrication includes the steps of forming a dielectric layer on a first surface of a semiconductor wafer having a plurality of laterally distributed semiconductor devices selectively interconnected on the first surface and bonding a support substrate to the first surface of the semiconductor wafer on the dielectric layer to form a composite structure. A portion of the semiconductor wafer from a second surface which is opposite the first surface is removed and the second surface of the semiconductor wafer is processed. Processing of the second surface optionally includes the formation of isolation trenches electrically isolating the laterally distributed semiconductor devices.

Abstract: In some embodiments, a light bulb for an electrodeless discharge lamp has a protuberance such that the cold spot of the bulb is located in the protuberance. The protuberance is spaced from the induction coil of the lamp so as to be easily accessible. Hence the cold spot temperature is easy to measure and control. In some embodiments, heat sinks are provided to cool the light bulb. An active control element including a Peltier element is provided to control the cold spot temperature.

Abstract: A method and apparatus for manufacturing a hollow plastic product is provided. In accordance with one aspect, into a mold half having a tubular groove portion and a projecting groove portion which projects outwardly from the tubular groove section is supplied a parison into the tubular groove portion and a clump of molding material into the projecting groove portion, and when blow molding is carried out by introducing a pressurized gas into the parison, the clump becomes integrated with the parison thereby providing a plastic product of unitary structure. In accordance with another aspect of the present invention, a parison extrusion nozzle is provided with at least two passages each of which is connected, preferably through a valve, to a corresponding dispensing unit for dispensing a desired molding material. A control unit is provided as connected to each of the dispensing units to control the supply of molding material so that there is obtained a parison having regions of different molding materials.

Abstract: In the preferred embodiment, the outputs of a plurality of analog signal generators are connected to a single wire (the analog bus). Each analog signal generator is addressable by a unique code provided to its respective address input terminals. A host controller selectively addresses only one of the analog signal generators such that an output of only one of the analog signal generators is applied to the analog bus at a time. In this manner, a single wire may be used to transmit a plurality of analog signals to a receiver. In one embodiment, the receiver is a MUX having an output connected to an ADC.

Abstract: A method for manufacturing a capacitor includes the steps of a) forming a first sacrificial layer over the etching stop layer; b) partially removing the first sacrificial layer, the etching stop layer, and the dielectric layer to form a contact window, c) forming a first conducting layer over the first sacrificial layer and in the contact window, d) forming a second sacrificial layer over the first conducting layer, e) partially removing the second sacrificial layer, the first conducting layer, and the first sacrificial layer to expose a portion of the first sacrificial layer, f) forming a second conducting layer alongside the second sacrificial layer, the first conducting layer, and the portion of the first sacrificial layer, and g) removing the first and second sacrificial layers to expose the etching stop layer, wherein the remained first conducting layer and the second conducting layer construct a capacitor plate with a generally crosssectionally modified H-shaped structure.

Abstract: The present invention relates to ignition circuitry for a plasma generator. A discharge is created by application of a high frequency or high voltage dc ignition pulse between an electrode and a first nozzle. Following ignition, the discharge is redirected to a second nozzle for the purpose of moving the plasma flow from the ignition zone into the zone of application to the workpiece. The present invention is directed to plasma ignition circuitry for improving this performance. Positive thermal coefficient ("PTC") resistance is shown to be useful in reliably and reproducibly switching the arc. Alternative embodiments of the present invention relate to switching the plasma from a first nozzle to a second nozzle then sequentially to additional nozzles downstream in the flow of plasma gas in which PTC resistance is used to reliably and reproducibly effect the switching.

Abstract: A power divider includes an input port, a first output port, a second output port, a first transformer coupled between the input port and the first output port, and a second transformer coupled between the input port and the second output port. The first and second transformers each incorporates a low pass filter. The power divider further includes a ground plate disposed adjacent to the first and second transformers. The ground plate is capacitively coupled to the low pass filters of the first and second transformers for enhancing the low pass filtering characteristics of the power divider. The power divider provides low pass filtering capability while achieving a significant size reduction over conventional power dividers.

Abstract: An electrochemical procedure is employed to selectively remove certain material from a structure without significantly electrochemically attacking other material of the same chemical type as the removed material. The material to be removed constitutes part or all of an electrically non-insulating region (52C). The material which is of the same chemical type as the removed material but which is not to be significantly electrochemically attacked during the removal procedure constitutes part or all of another electrically non-insulating region (52A) electrically decoupled from the first-mentioned non-insulating region. The electrochemical removal procedure is performed with an organically based electrolytic solution containing organic solvent and acid.