Abstract: A method of fabricating a planarized metal structure comprising the following steps. A structure is provided. A patterned dielectric layer is formed over the structure. The patterned dielectric layer having an opening formed therein and exposing at least a portion of the structure. A first-metal layer is formed over the patterned dielectric layer filling the opening. The first-metal layer including at least a doped metal portion adjacent the patterned dielectric layer. The doped metal portion being doped with a second-metal. The structure is annealed to form a second-metal oxide layer adjacent the patterned dielectric layer. The first-metal layer and the second-metal oxide layer are planarized using only a electropolishing process to remove the excess of the first-metal layer and the second-metal oxide layer from over the patterned dielectric layer and leaving a planarized metal structure within the opening.

Abstract: A method of forming a bump structure, comprising the following steps. A structure having an exposed first conductive structure is provided. A first photoresist layer is formed over the structure and the exposed first conductive structure. A second capping photoresist layer is formed over the first photoresist layer. The first and second photoresist layers being comprised of different photoresist materials. The first and second photoresist layers are patterned to form an opening through the first and second photoresist layers and over the first conductive structure. The second capping photoresist layer prevents excessive formation of first photoresist layer residue during processing. A second conductive structure is formed within the opening. The first and second patterned photoresist layers are stripped. The second conductive structure is reflowed to form the bump structure.

Abstract: A method of forming a top-metal fuse structure comprising the following steps. A structure having an intermetal dielectric layer is formed thereover, the structure including a fuse region and an RDL/bump/bonding pad region. A composite metal layer is formed over the intermetal dielectric layer. The composite metal layer including a second metal layer sandwiched between upper and lower first metal layers. The upper first metal layer is patterned to form an upper metal layer portion within the RDL/bump/bonding pad region. The second metal layer and the lower first metal layer are patterned: (1) within the RDL/bump/bonding pad region to form an RDL/bump/bonding pad; the RDL/bump/bonding pad having a patterned second metal layer portion/lower first metal portion with a width greater than that of the upper metal layer portion and forming a step profile; and (2) within the fuse region to form the top-metal fuse structure. The RDL/bump/bonding pad structure includes a step profile.

Abstract: A method of reducing substrate coupling and noise for one or more RFCMOS components comprising the following steps. A substrate having a frontside and a backside is provided. One or more RFCMOS components are formed over the substrate. One or more isolation structures are formed within the substrate proximate the one or more RFCOMS components. The backside of the substrate is etched to form respective trenches within the substrate and over at least the one or more isolation structures. The respective trenches are filled with dielectric material whereby the substrate coupling and noise for the one or more RFCMOS components are reduced.

Abstract: A method of gate patterning, including the following steps. A semiconductor structure having an upper silicon layer is provided. The semiconductor structure has a gate conductor region. A first gate oxide layer is formed over the semiconductor structure. A polysilicon layer is formed over the first gate oxide layer. A patterned oxide mask and photoresist layer are formed over the polysilicon layer within the gate conductor region leaving unmasked polysilicon layer portions and unmasked first gate oxide layer portions. An oxygen implant is conducted within the unmasked polysilicon layer portions proximate the unmasked first gate oxide layer portions. The patterned photoresist mask is removed. The structure is annealed to form second gate oxide portions within the unmasked polysilicon layer portions over the unmasked first gate oxide layer portions.

Abstract: A stacked die design, and a method of forming the same, comprising: a substrate having a lower surface and an upper surface; a lower die connected to the substrate; a thermally conductive metal interposer thermally connected to the lower die and/or the substrate; and an upper die thermally connected to the metal interposer. The lower die and the upper die being spaced apart and comprising a stacked die whereby any heat generated by the upper die is transferred to the substrate by the metal interposer.

Abstract: A method of clearing photoresist on a wafer edge, including the following steps. A wafer having a upper exposed conductive layer is provided. The wafer having a center, an edge and a ring-shaped area proximate the wafer edge. A photoresist layer is formed upon the exposed conductive layer. The photoresist layer is removed from within the ring-shaped area by a rinse process to expose the conductive layer within the ring-shaped area. An oxygen diffusion barrier layer is formed over the photoresist layer.

Abstract: A high performance 1T RAM cell in a system-on-a-chip is formed using an asymmetric LDD structure that improves pass gate performance and storage node junction leakage. The asymmetric LDD structure is formed using selective ion implantation of the core and I/O LDDs. The node junctions are both pocket implant-free and source/drain implant-free. Further, silicide formation is avoided within the storage node junctions by forming nearly merged sidewall spacers within the node junctions and by forming optional blocking portions over the nearly merged sidewall spacers.

Abstract: A method of fabricating an RF lateral MOS device, comprising the following steps. A substrate having a gate oxide layer formed thereover is provided. A first layer of polysilicon is formed over the gate oxide layer. A second layer of material is formed over the polysilicon layer. The polysilicon and the second layer of material are patterned to form a gate having exposed sidewalls with the gate having a lower patterned polysilicon layer and an upper patterned second material layer. Sidewall spacers are formed on the exposed sidewalls of the gate. The upper patterned second material layer of the gate is removed to form a cavity above the patterned polysilicon layer and between the sidewall spacers. A planarized copper plug is formed within the cavity.

Abstract: A method of forming a high fMAX deep submicron MOSFET, comprising the following steps of. A substrate having a MOSFET formed thereon is provided. The MOSFET having a source and a drain and including a silicide portion over a gate electrode. A first ILD layer is formed over the substrate and the MOSFET. The first ILD layer is planarized to expose the silicide portion over the gate electrode. A metal gate portion is formed over the planarized first ILD layer and over the silicide portion over the gate electrode. The metal gate portion having a width substantially greater than the width of the silicide portion over the gate electrode. A second ILD layer is formed over the metal gate portion and the first ILD layer. A first metal contact is formed through the second ILD layer contacting the metal gate portion, and a second metal contact is formed through the second and first ILD layers contacting the drain completing the formation of the high fMAX deep submicron MOSFET.

Abstract: A method of structures having dual gate oxide thicknesses, comprising the following steps. A substrate having first and second pillars is provided. The first and second pillars each having an outer side wall and an inner side wall. At least one of the outer or inner side walls of at least one of the first and second pillars is/are masked leaving at least one of the outer or inner side walls of at least one of the first and second pillars exposed. Dopants are then implanted through the at least one of the exposed outer or inner side walls modifying the surface of the at least one of the doped exposed outer or inner side walls. The at least one of the masked outer or inner side walls of at least one of the first and second pillars is/are unmasked.

Abstract: A method of forming narrow gates comprising the following steps. A substrate is provided having an overlying Si3N4 or an SiO2/Si3N4 stack gate dielectric layer. A gate material layer is formed over the gate dielectric layer. A hard mask layer is formed over the gate material layer. The hard mask layer and the gate material layer are patterned to form a hard mask/gate material layer stack. A planarized dielectric layer is formed surrounding the hard mask/gate material layer stack. The patterned hard mask layer is removed from over the patterned gate material layer to form a cavity having exposed dielectric layer side walls. Masking spacers are formed on the exposed dielectric layer side walls over a portion of the patterned gate material layer. The patterned gate material layer is etched using the masking spacers as masks to expose a portion of the gate dielectric layer. The planarized dielectric layer is removed. The masking spacers are removed to form narrow gates comprising gate material.

Abstract: A method of fabricating dual gate oxide thicknesses comprising the following steps. A substrate is provided having a first pillar and a second pillar. A gate dielectric layer is formed over the substrate and the first and second pillars. First and second thin spacers are formed over the gate dielectric layer covered side walls of the first and second pillars respectively. The second pillar is masked leaving the first pillar unmasked. The first thin spacers are removed from the unmasked first pillar. The mask is removed from the masked second pillar. The structure is oxidized to convert the second thin spacers to second preliminary gate oxide over the previously masked second pillar and to form first preliminary gate oxide over the unmasked first pillar. The second gate oxide over the second pillar being thicker than the first gate oxide over the first pillar.

Abstract: A method of fabricating a solder bump including the following steps. A UBM over a substrate.having an exposed pad portion is provided. The UBM being in electrical contact with the pad portion. A first patterning layer is formed over the UBM. The first patterning layer including a photosensitive material sensitive to light having a first wavelength. A second patterning layer is formed over the first patterning layer. The second patterning layer including a photosensitive material sensitive to light having a second wavelength. The first patterning layer is selectively exposed with the light having the first wavelength, leaving a first unexposed portion substantially centered over the pad portion between first exposed portions. The second patterning layer is selectively exposed with the light having the second wavelength, leaving a second unexposed portion wider than, and substantially centered over, the first unexposed portion of the exposed first patterning layer.

Abstract: A square poly-spacer and making of the same are disclosed. The square poly-spacer is formed adjacent a floating poly-gate sharing a common source line with another floating poly-gate. The common source line comprises polysilicon and is separated from the floating poly-gate by an intervening oxide spacer. The square poly-spacer is also separated from the floating gate by an intergate oxide layer, and serves as a control gate and communicates with a salicided word line formed over the square top of the poly-spacer. It is shown that a square poly-spacer can be formed advantageously by first chemical mechanical polishing a poly spacer and then performing an etch back of the polysilicon, rather than just performing an etch back only. The square top, rather than the continuously contoured sloping wall, prevents the bridging that can occur over a curved poly spacer to the substrate when a portion of the poly spacer surface is salicided to obtain a well behaving word line.

Abstract: A method for cleaning residual material from a chemical vapor deposition (CVD) apparatus in situ employing dry etching. There is first employed a high density plasma chemical vapor deposition (HDP-CVD) method to deposit layers of silicon oxide material upon substrates within a chemical vapor deposition reactor apparatus. After removal of substrates, the reactor chamber is closed off. The interior of the reactor is then filled with a gas and a plasma formed therewithin, to which oxygen is added and the reactor allowed to come to an increased temperature and bake for a period of time. The reactor power is then turned off and the reactor evacuated. There is then carried out a normal cleaning step within the reactor chamber employing a reactive gas such as NF3, with greater cleaning efficiency due to the increased temperature caused by the baking step.

Abstract: A chemical mechanical polish (CMP) planarizing method for forming a chemical mechanical polish (CMP) planarized layer within a microelectronic fabrication. There is first provided a substrate. There is then formed over the substrate a chemical mechanical polish (CMP) substrate layer having an aperture formed therein. There is then formed upon the chemical mechanical polish (CMP) substrate layer and completely filling the aperture within the chemical mechanical polish (CMP) substrate layer a blanket chemical mechanical polish (CMP) planarizable layer. There is then chemical mechanical polish (CMP) planarized, while employing a chemical mechanical polish (CMP) planarizing method, the blanket chemical mechanical polish (CMP) planarizable layer to form within the aperture from the blanket chemical mechanical polish (CMP) planarizable layer a patterned chemical mechanical polish (CMP) planarized layer.

Abstract: A method for fabricating a via openings, comprising the following steps. A semiconductor structure is provided. A low-k layer is formed upon the semiconductor structure. A via opening is formed within the low-k layer. An inert polymer liner layer is formed upon the low-k layer and within the via opening. A photoresist layer is formed upon the inert polymer liner layer, filling the inert polymer lined via opening. The inert polymer liner layer preventing adverse chemical reactions between the photoresist layer and portions of the low-k layer. The photoresist layer is patterned to expose the inert polymer lined via opening and portions of the inert polymer lined low-k layer adjacent the via opening. The exposed inert polymer lined via opening and portions of the inert polymer lined low-k layer adjacent the via opening and the portions of the inert polymer liner layer upon the via opening and portions of the inert polymer lined low-k layer adjacent the via opening are etched to form a structure opening.

Abstract: A method for etching a pattern within a silicon containing dielectric layer upon a substrate employed within a microelectronics fabrication, employing a plasma activated reactive gas mixture, with layer material etch rate, etch rate ratio and pattern aspect ratio controlled by controlling the gas composition. There is provided a silicon substrate formed upon it a patterned microelectronics layer over which is formed a silicon containing dielectric layer. There is placed the silicon substrate within a reactor chamber equipped with electrodes which is evacuated. There is then filled the reactor chamber with a reactive gas mixture consisting of an oxidizing gas and two reactive gases. There may be optionally included in the reactive gas mixture nitrogen and inert gases for control purposes, but excluded from the reactive gas mixture are oxidizing gases containing carbon and oxygen.

Abstract: A method of forming an HDP CVD oxide layer over a metal line structure, comprising the following steps. A semiconductor structure having metal lines formed thereon to form a metal line structure is provided. The metal lines having exposed sidewalls. The metal line structure is treated with N2O to form a layer of Al2O3 on each of the metal line exposed sidewalls to form a N2O treated metal line structure. An HDP CVD oxide layer is formed over the N2O treated metal line structure to form a resulting metal line structure. Whereby the resulting metal line structure is free of metal voids.