Abstract: A method of fabricating doped polysilicon structures comprising the following steps. A substrate is provided and an undoped polysilicon layer is formed over the substrate. The undoped polysilicon layer is patterned to form at least one undoped polysilicon structure within an N area and at least one undoped polysilicon structure within a P area. The at least one undoped polysilicon structure within the N area is masked, leaving exposed an upper portion of the other at least one undoped polysilicon structure within the P area. The exposed at least one undoped polysilicon structure within the P area is doped to form a P-doped polysilicon structure. An upper portion of the masked at least one undoped polysilicon structure within the N area is unmasked and exposed, and the P-doped polysilicon structure is masked. The exposed at least one undoped polysilicon structure within the N area is doped to form an N-doped polysilicon structure to complete fabrication of the doped polysilicon structures.

Abstract: A method to fabricate a bonding pad structure including the following steps. A substrate having a top metal layer and a passivation layer overlying the top metal layer is provided. The top metal layer being electrically connected to a lower metal layer by at least one metal via within a metal via area. The substrate includes a low-k dielectric layer at least between the lower metal layer and the top metal layer. The passivation layer is etched within the metal via area to form a trench exposing at least a portion of the top metal layer. A patterned, extended bonding pad is formed over the etched passivation layer and lining the trench. The extended bonding pad having a portion that extends over a peripheral planar area of the substrate adjacent the trench not within the metal via area. A wire bond is bonded to the extended bonding pad at the peripheral planar area portion to form the bonding pad structure.

Abstract: A method of fabricating an STI, comprising the following steps. A silicon structure having a pad oxide layer formed thereover is provided. An undoped poly buffer layer is formed over the pad oxide layer. A hard mask layer is formed over the undoped poly buffer layer. The hard mask layer, the undoped poly buffer layer and the pad oxide layer are patterned to form an opening exposing a portion of the silicon structure within an active area. The opening having exposed side walls. Inorganic spacers are formed over the exposed side walls. Using the patterned hard mask layer and the spacers as hard masks, the silicon structure is etched to form an STI opening within the active area. The inorganic spacers are removed exposing the upper corners of the STI opening. Using an oxidation process, a liner oxide layer is formed within the STI opening, over the upper corners of the STI opening and at least the patterned undoped poly buffer layer exposed by the removal of the inorganic spacers.

Abstract: A method of bi-layer top surface imaging, comprising the following steps. A structure having a lower layer formed thereover is provided. An upper silicon-containing photoresist layer is formed upon the lower layer. The upper silicon-containing photoresist layer is selectively exposed to form upper silicon-containing photoresist layer exposed portions. The upper silicon-containing photoresist layer exposed portions and the portions of the lower layer below the upper silicon-containing photoresist layer exposed portions are removed using an O2-free N2/H2 plasma etch.

Abstract: A method for recycling a fluid in a wet bench tank recycling device, comprising the following steps. An outer recycle tank is provided having sides and a bottom. The outer recycle tank holding outer recycle tank fluid. An inner process tank is provided having sides and a sieved bottom housed within the outer recycle tank. The inner process tank sides being spaced apart from the sides of the outer recycle tank sides and the inner process tank bottom being spaced apart from the outer recycle tank bottom. The inner process tank holding inner process tank fluid. A wide area filter fitted within the inner process tank proximate the inner process tank sieved bottom is provided. A vertically moveable top cover is provided at an uppermost position and fitted between the inner process tank sides and the outer recycle tank sides. The top cover having one-way valves therein that permit flow of fluid only downward through the one-way valves. The vertically moveable top cover having a top and a bottom.

Abstract: A method for forming FET devices with attenuated gate induced drain leakage current. There is provided a silicon semiconductor substrate employed within a microelectronics fabrication. There is formed within the silicon substrate field oxide (FOX) dielectric isolation regions defining an active silicon substrate device area. There is formed over the substrate a silicon oxide gate oxide insulation layer employing thermal oxidation. There is then formed over the silicon oxide gate oxide insulation layer a patterned polycrystalline silicon gate electrode layer. There is then thermally oxidized the substrate and polycrystalline silicon gate electrode to form a thicker silicon oxide layer at the edge of the gate electrode and in the adjacent silicon substrate area. There is then etched back the thicker silicon oxide layer from the silicon substrate area adjacent to the gate electrode.

Abstract: A method of integrated circuit component integration in copper interconnects, including the following steps of the first embodiment. A wafer is provided having an exposed top-most planar copper interconnect. The wafer being divided into one or more areas selected from the group consisting of: a spiral inductor area having an exposed planar copper interconnect bottom half of a stacked spiral inductor; a MIM capacitor area having an exposed planar copper interconnect bottom plate and an exposed planar copper interconnect contact point of a MIM capacitor; and a precision resistor area having a two exposed planar copper interconnect routing points of a precision resistor. A spiral inductor is formed within the spiral inductor area; a MIM capacitor is formed within the MIM capacitor area; and a precision resistor is formed within the precision resistor area.

Abstract: A method of fabricating at least one metal interconnect including the following steps. A structure having at least one exposed conductive structure is provided. A non-stick material layer is formed over the structure and the at least one exposed conductive structure. The non-stick material layer having an upper surface. The non-stick material layer is patterned to form a patterned non-stick material layer having at least one trench therethrough exposing at least a portion of the at least one conductive structure. A metal interconnect is formed in contact with the exposed portion of the at least one conductive structure within the at least one trench wherein the non-stick properties of the patterned non-stick material layer prevent accumulation of the metal comprising the metal interconnect upon the patterned upper surface of the patterned non-stick material layer. The at least one metal interconnect having an upper surface. The patterned non-stick material layer is removed.

Abstract: A method for forming a via through a dielectric layer. There is first provided a substrate. There is then formed over the substrate a patterned conductor layer. There is then formed covering the patterned conductor layer a dielectric layer. There is then formed through the dielectric layer a via to access the patterned conductor layer, where the via is incompletely landed upon the patterned conductor layer. There is then purged the via while employing a vacuum purging method to form a purged via. There is then passivated the purged via and passivated the patterned conductor layer exposed within the purged via while employing a plasma passivation method to form a plasma passivated purged via and a plasma passivated patterned conductor layer. Finally, there is then formed into the plasma passivated purged via a conductor stud layer.

Abstract: A method for completely removing dielectric layers formed selectively upon a substrate employed within a microelectronics fabrication from regions wherein closely spaced structures such as self-aligned metal silicide (or salicide) electrical contacts may be fabricated, with improved properties and with attenuated degradation. There is first provided a substrate with employed within a microelectronics fabrication having formed thereon patterned microelectronics layers with closely spaced features. There is then formed a salicide block layer employing silicon oxide dielectric material which may be selectively doped. There is then formed over the substrate a patterned photoresist etch mask layer. There is then etched the pattern of the patterned photoresist etch mask layer employing dry plasma reactive ion etching. An anhydrous etching environment is then employed to completely remove the silicon oxide dielectric salicide block layer with attenuated degradation of the microelectronics fabrication.

Abstract: A method of fabricating a semiconductor transistor device comprising the following steps. A semiconductor structure is provided having an upper silicon layer, a pad dielectric layer over the upper silicon layer, and a well implant within a well region in the upper silicon layer. A lower SiN layer is deposited and patterned over the pad dielectric layer to define a lower gate area. The pad dielectric layer and the upper silicon layer within the lower gate area is etched to form a lower gate trench having a predetermined width. A lower gate portion is formed within the lower gate trench. An upper oxide layer is formed over the lower SiN layer. An upper SiN layer is formed over the upper oxide layer. The upper SiN layer is etched to define an upper gate trench having a predetermined width greater than the lower gate trench predetermined width. An upper gate portion is formed within the upper gate trench, wherein the lower and upper gate portions form a T-shaped gate.

Abstract: A method for forming upon a substrate employed within a microelectronics fabrication a silicon nitride dielectric layer with attenuated defects and inhomogeneities. There is provided one or more substrates. There is then provided a reactor tube which is part of an apparatus suitable for providing various gases at elevated temperatures. There is then purged the reactor tube with an inert gas in a low temperature cycle purge (LTCP) step at a temperature below deposition temperature. There is then placed the substrate(s) within a reactor tube. There is then deposited a silicon nitride dielectric layer upon the substrate(s), employing silane and ammonia gases employing a low pressure chemical vapor deposition (LPCVD) method. There is then purged the reaction tube at a temperature below the deposition temperature, followed by removal of the substrate carrier with attenuated formation of particulates and inhomogeneities within and about the silicon nitride layer and reaction tube.

Abstract: A dry cleaning method for use in semiconductor fabrication, including the following steps. An etched metallization structure is provided and placed in a processing chamber. The etched metallization structure is cleaned by introducing a fluorine containing gas/oxygen containing gas mixture into the processing chamber proximate the etched metallization structure without the use of a downstream microwave while applying a magnetic field proximate the etched metallization structure and maintaining a pressure of less than about 50 millitorr within the processing chamber for a predetermined time.

Abstract: A method to fabricate a 1T-RAM device, comprising the following steps. A semiconductor substrate having an access transistor area and an exposed bottom plate within a capacitor area proximate the access transistor area is provided. A gate with an underlying gate dielectric layer within the access transistor area are formed. The gate and underlying gate dielectric layer having sidewall spacers formed over their respective exposed side walls. A top plate with an underlying capacitor layer over the bottom plate within the capacitor area are formed. The top plate and underlying capacitor layer having sidewall spacers formed over their respective exposed side walls. A patterned resist protect oxide (RPO) layer is formed over at least the drain of the structure not to be silicided. Metal silicide portions are formed over the structure not protected by the RPO layer.

Abstract: A method of improving adhesion of a surface including the following steps. A structure having an upper surface is provided. A composite anchor layer is formed over the upper surface of the structure. The composite anchor layer including at least an upper anchor sub-layer and a lower anchor sub-layer. The upper anchor sub-layer is patterned to form a dense pattern of upper sub-anchors. The lower anchor sub-layer is then patterned using the upper sub-anchors as masks to form lower sub-anchors. The respective upper sub-anchors and lower sub-anchors form a dense pattern of anchors whereby the dense pattern of anchors over the upper surface improve the adhesion of the surface.

Abstract: A method for forming a patterned microelectronic layer. There is first provided a substrate. There is then formed over the substrate a multi-layer stack layer comprising: (1) a first lower microelectronic layer; (2) a second intermediate patterned microelectronic layer formed over the first lower microelectronic layer; and (3) a third upper patterned microelectronic layer formed over the second intermediate patterned microelectronic layer, where the first lower microelectronic layer and the third upper patterned microelectronic layer are susceptible to etching within a first etchant. There is then formed encapsulating the first lower microelectronic layer and at least portion of the second intermediate patterned microelectronic layer while leaving exposed at least a portion of the third upper patterned microelectronic layer an encapsulating layer.

Abstract: A method of fabricating an isolated vertical transistor comprising the following steps. A wafer having a first implanted region selected from the group comprising a source region and a drain region is provided. The wafer further includes STI areas on either side of a center transistor area. The wafer is patterned down to the first implanted region to form a vertical pillar within the center transistor area using a patterned hardmask. The vertical pillar having side walls. A pad dielectric layer is formed over the wafer, lining the vertical pillar. A nitride layer is formed over the pad dielectric layer. The structure is patterned and etched through the nitride layer and the pad dielectric layer; and into the wafer within the STI areas to form STI trenches within the wafer. The STI trenches are filled with insulative material to form STIs within STI trenches. The patterned nitride and pad dielectric layers are removed. The patterned hardmask is removed.

Abstract: A fusible link device and a method of making same. The fusible link device comprising a poly layer having a center undoped portion and two doped end portions. The center undoped portion having a first resistance and the two doped end portions each having a second resistance that is lower than the first resistance. A silicide layer is formed over the poly layer with the silicide layer having a third resistance lower than the second resistance. The silicide layer agglomerating to form an electrical discontinuity within a discontinuity area in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased. The agglomeration of the silicide layer occurring over the center undoped portion of the poly layer. Contacts are electrically coupled to the two doped poly layer end portions for receiving the programming potential.

Abstract: A method for forming a composite dielectric layer comprising a low dielectric constant dielectric layer upon a substrate employed within a microelectronics fabrication. There is provided a patterned microelectronics layer upon a substrate employed within a microelectronics fabrication. There is then formed upon the microelectronics substrate a low dielectric constant dielectric layer. There is then treated the low dielectric constant dielectric layer with a plasma, forming a plasma treated low dielectric constant dielectric layer. There is then formed upon the plasma treated low dielectric constant dielectric layer a silicon containing dielectric layer with enhanced adhesion thereupon.

Abstract: A method to fabricate a metal via structure having improved electromigration resistance, comprising the following steps. A semiconductor structure having an exposed metal interconnect structure therein is provided. The metal interconnect structure including a metal via portion. A capping layer is formed over the metal interconnect structure. A via pattern structure is formed over the capping layer. The via pattern structure having a via pattern hole aligned with the metal via portion of the metal interconnect structure. Ions are implanted through the via pattern hole into the metal via portion, and any portion of the metal interconnect structure above the metal via portion. Whereby the metal via portion and the portion of the metal interconnect structure above the metal via portion have improved electromigration resistance.