Abstract: A computer readable medium encoded with a computer program for handling transaction messages in asynchronous data replication in a database system is disclosed. The computer program provides a high speed parallel apply of transactional changes to a target node such that the parallel nature of the application of changes does not compromise the integrity of the data. The computer program detects, tracks, and handles dependencies between transaction messages to be applied to the target node. If a transaction message has a dependency on one or more preceding transaction messages whose applications have not yet completed, that transaction message is held until the application completes. In addition, the computer program requires significantly less overhead than conventional approaches.

Abstract: A mechanism is provided for adapting a network topology, in which the network topology comprises a plurality of points, a plurality of connections, each connection connecting a pair of points, and a zoneset comprising a plurality of zones, each zone defining a series of points that are connected. The mechanism performs operations of receiving one or more user inputs, each user input comprising a change to a zone, performing an analysis of the or each user input, to determine one or more consistent universal changes to the zoneset, presenting an output to the user comprising one or more of the determined consistent universal changes to the zoneset, receiving a selection user input selecting a presented consistent universal change to the zoneset, and changing the zoneset according to the selected consistent universal change to the zoneset.

Abstract: A hardware wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism looks ahead in a thread for programming idioms that indicates that the thread is waiting for an event. The wake-and-go mechanism performs a look-ahead polling operation for each of the programming idioms. If each of the look-ahead polling operations fails, then the wake-and-go mechanism updates a wake-and-go array with a target address associated with the event for each recognized programming idiom.

Abstract: A mechanism for automatic reallocation of shared external storage structures is provided. The shared external storage divides the dynamically allocable storage into fixed sized blocks referred to as allocation units. To create an object of a specific type, the shared external storage uses some number of allocation units. If the object will fit in one allocation unit, then it is placed in one allocation unit. If the object is larger than one allocation unit, then the appropriate number of allocation units is obtained and chained together to contain all of the information of the required object. When an object so allocated is no longer needed, the shared external storage breaks the object down to a set of one or more fixed sized allocation units. The shared external storage then returns the allocation units to the pool of available objects.

Abstract: Mechanisms are provided in a design environment for eliminating, coalescing, or bypassing ports. The design environment comprises one mechanism to eliminate unnecessary ports in arrays using disabled and disconnected pin information. The design environment may comprise another mechanism to combine and reduce the number of array ports using address comparisons. The design environment may comprise another mechanism to combine and reduce the number of array ports using disjoint enable comparisons. The design environment may comprise one mechanism to combine and reduce the number of array ports using “don't care” computations. The design environment may comprise another mechanism to reduce the number of array ports through bypassing write-to-read paths around arrays.

Abstract: Mechanisms are provided for characterizing long range variability in integrated circuit manufacturing. A model derivation component tests one or more density pattern samples, which are a fabricated integrated circuits having predetermined pattern densities and careful placement of current-voltage (I-V) sensors. The model derivation component generates one or more empirical models to establish range of influence of long range variability effects in the density pattern sample. A variability analysis component receives an integrated circuit design and, using the one or more empirical models, analyzes the integrated circuit design to isolate possible long range variability effects in the integrated circuit design.

Abstract: A wake-and-go mechanism is provided for a microprocessor. The wake-and-go mechanism looks ahead in the instruction stream of a thread for programming idioms that indicate that the thread is waiting for an event. if a look-ahead polling operation succeeds, the look-ahead wake-and-go engine may record an instruction address for the corresponding idiom so that the wake-and-go mechanism may have the thread perform speculative execution at a time when the thread is waiting for an event. During execution, when the wake-and-go mechanism recognizes a programming idiom, the wake-and-go mechanism may store the thread state in the thread state storage. Instead of putting the thread to sleep, the wake-and-go mechanism may perform speculative execution.

Abstract: A mechanism for operating a virtual memory is provided in an operating system. The mechanism detects the existence of a central memory loan pool, identifies a segment of memory that is loanable, and transmits an indicator that the segment is available for loaning to the memory loan pool. The operating system contributing memory can monitor its actual memory capacity and reclaim the loaned segment if the amount of memory available to the loaning operating system (OS) gets below a predetermined value.

Abstract: A wake-and-go mechanism is provided with a central repository wake-and-go array for a multiple processor data processing system. The wake-and-go mechanism recognizes a programming idiom that indicates that a thread running on a processor within the multiple processor data processing system is waiting for an event. The wake-and-go mechanism updates a central repository wake-and-go array with a target address associated with the event. Each entry in the central repository wake-and-go array may include a thread identification (ID), a central processing unit (CPU) ID, the target address, the expected data, a comparison type, a lock bit, a priority, and a thread state pointer, which is the address at which the thread state information is stored.

Abstract: Mechanisms are provided in a design environment for minimizing memory array representations for enhanced synthesis and verification. The design environment comprises one mechanism to compress the width of arrays using disconnected pin information. The design environment comprises another mechanism to simplify the enable conditions of array ports using “don't care” computations. The design environment comprises yet another mechanism to reduce address pins from an array through analysis of limitations of readable addresses.

Abstract: The advanced management module services in a data processing system are configured to determine the system load and provide an input to the early power off warning detection logic that evaluates the power system state to detect a condition when power resources are insufficient to maintain the write caching storage system power within defined acceptable limits. The early power off warning detection logic generates a notification based on the system load and the available power supply resources to maintain maximum availability and reliability characteristics.

Abstract: A system and method for interfacing with a network component is described. One embodiment includes an electronic method that accesses a network component; retrieves a command set from the network component; generates a configuration schema corresponding to the network component using the retrieved command set; and then stores the generated configuration schema.

Abstract: Mechanisms are provided in a design environment for array concatenation. The design environment comprises one mechanism to concatenate arrays with enable- and address-compatible ports, thereby reducing the number of arrays in a netlist. The design environment comprises another mechanism to migrate read ports from one array to another based upon compatible enable-, address-, and data-compatible write ports, thereby reducing the number of arrays in a netlist. The design environment comprises yet another mechanism to eliminate unnecessary arrays.

Abstract: Mechanisms are provided for creating shift register definition from high-level model using high-level model simulation. The mechanisms initialize all potential scan chain latches, identify the latches in a given scan chain, and separate the scan chain latches into chunks. For each chunk, the mechanisms identify the latches within the chunk that change at each shift. The mechanisms isolate the scan path latch when divergence occurs.

Abstract: A mechanism is provided for distributing file fragments in the background of a segmented peer-to-peer network using list passing between peers. Rather than trading actual content, peers may trade file names or file fragment identifiers. Upon receiving a new file name or identifier, a peer may request that file from the network, either in the background or the foreground. For example, once a client begins background file sharing in a swarm, the client may propagate file information for files it possesses to all or a portion of the peers in a swarm. Those clients then have the file information for a file without the user having to locate and specifically request that file. The file list may piggyback on a file fragment that is transferred as a result of a file sharing request.

Abstract: A mechanism for initializing shared memories for sharing endpoints across a plurality of root complexes is provided. A multi-root PCIe manager (MR-PCIM) initializes the shared memory between root complexes and endpoints by discovering the PCIe switch fabric by traversing all the links accessible through the interconnected switches of the PCIe switch fabric. As the links are traversed, the MR-PCIM compares information obtained for each of the root complexes and endpoints to determine which endpoints and root complexes reside on the same blade. A virtual PCIe tree data structure is then generated that ties the endpoints available on the PCIe switch fabric to each root complex. The MR-PCIM, or a single-root PCIe manager (SR-PCIM), may then assign each endpoint and root complex a base and limit within the PCIe memory address space the endpoint belongs to.

Abstract: A mechanism for managing locks for one or more resources in a distributed system including multiple distributed computing nodes, is provided. One implementation involves maintaining a database as a shared storage accessible by plural participating nodes for storing shared lock information, each participating node locally managing a local list of locks, the participating nodes cooperating in providing decentralized lock management across the nodes using the local and shared lock information, to achieve granting and releasing of locks for synchronizing access to one or more resources.

Abstract: A battery conservation component synchronizes with a user's schedule or calendar. The battery conservation component may disable functions or features to ensure that the device has sufficient battery life for selected calendar events. The battery conservation component may warn the user if a battery charge is necessary to make selected calendar events. The battery conservation component may be applied to a wide variety of portable devices with time-sensitive events. For example, the battery conservation component may be applied to a device with vehicle navigation and estimate time-sensitive events based on waypoints in the vehicle's route. The battery conservation component may synchronize with a user's travel itinerary. Alternatively, the battery conservation component may suggest alternative functions or features based on a time-sensitive event, such as suggesting a shorter movie on a flight or road trip.

Abstract: A system for handling denormal floating point operands when the result must be normalized. A leading zero counter (lzc) on the operand B (opB) is used to limit alignment shifts when opB is denormal but is much greater than the product of operands A and C, i.e. AC. By limiting the additional shift of B during normalization, by the number of leading zeros in opB, no increase is needed in the output bus of the alignment shifter. Furthermore, the additional shift may be done either in the alignment shifter, or postponed to a later stage in the pipeline, where the result is normalized.

Abstract: A block matrix multiplication mechanism is provided for reversing the visitation order of blocks at corner turns when performing a block matrix multiplication operation in a data processing system. The mechanism increases block size and divides each block into sub-blocks. By reversing the visitation order, the mechanism eliminates a sub-block load at the corner turns. The mechanism performs sub-block matrix multiplication for each sub-block in a given block, and then repeats operation for a next block until all blocks are computed. The mechanism may determine block size and sub-block size to optimize load balancing and memory bandwidth. Therefore, the mechanism reduces maximum throughput and increases performance. In addition, the mechanism also reduces the number of multi-buffered local store buffers.