Abstract: A hardware wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism recognizes a programming idiom that indicates that a thread is waiting for an event. The wake-and-go mechanism updates a wake-and-go array with a target address associated with the event. The thread then goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The wake-and-go mechanism associates these storage addresses with the threads waiting for an even at the target addresses, and may wake the one or more threads waiting for the event.

Abstract: A mechanism is provided in a cache for emulating larger linesize in a substrate with smaller linesize using gang fetching and gang replacement. Gang fetching fetches multiple lines on a cache miss to ensure that all smaller lines that make up the larger line are resident in cache at the same time. Gang replacement evicts all smaller lines in cache that would have been evicted had the cache linesize been larger. The mechanism provides adaptive linesize using set dueling by dynamically selecting between multiple linsizes depending on which linesize performs the best at runtime. Set dueling dedicates a portion of sets of the cache to always use smaller linesize and dedicates one or more portions of the sets of cache to always emulate larger linesizes. One or more counters keep track of which linesize has the best performance. The cache uses that linesize for the remainder of the sets.

Abstract: Co-Optimization utilizing Symbolic Execution (COSE) works across components of an embedded design to optimize structures therein. COSE utilizes symbolic execution (SE) to analyze software components and defines a limited set of values that software feeds hardware as constraints. SE explores substantially all possible paths of execution of the code specifying a component. It accomplishes this by accumulating path conditions (PCs) and annotating them to the corresponding segments of the component. A PC is associated with a branch of code and consists of the conjunction of conditions over input and state variables necessary and sufficient for the branch to execute. These PCs define constraints that limit the set of values that software feeds hardware. These constraints are then propagated across the networks of the design and employ static analysis techniques such as constant propagation, redundancy removal, and don't care optimizations to reduce the hardware components.

Abstract: A mechanism is provided for providing an improved reconfigurable cache. The mechanism partitions a large cache into inclusive cache regions with equal-ratio size or other coarse size increase. The cache controller includes an address decoder for the large cache with a large routing structure. The cache controller includes an additional address decoder for the small cache with a smaller routing structure. The additional address decoder for the small cache reduces decode, array access, and data return latencies. When only a small cache is actively in use, the rest of the cache can be turned into low-power mode to save power.

Abstract: A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism detects a thread running on a first processing unit within a plurality of processing units that is waiting for an event that modifies a data value associated with a target address. The wake-and-go mechanism creates a wake-and-go instance for the thread by populating a wake-and-go storage array with the target address. The operating system places the thread in a sleep state. Responsive to detecting the event that modifies the data value associated with the target address, the wake-and-go mechanism assigns the wake-and-go instance to a second processing unit within the plurality of processing units. The operating system on the second processing unit places the thread in a non-sleep state.

Abstract: A non-volatile flash memory comprises a plurality of non-volatile memories where a first non-volatile memory is pre-programmed (erased) with all ones, and at least a second non-volatile memory is pre-programmed with a seed value that takes advantage of the reduced programming time for less than six zeros. When writing (programming) a data byte, the memory system looks up the data byte in one or more seed tables to determine a portion of non-volatile memory to which the memory system may write the data byte with a reduced programming time. The memory system then records the location of the data byte in an address translation table so the data byte may be accessed.

Abstract: A method, an apparatus, and a computer program are provided to account for data stored in Dynamic Random Access Memory (DRAM) write buffers. There is difficulty in tracking the data stored in DRAM write buffers. To alleviate the difficulty, a cache line list is employed. The cache line list is maintained in a memory controller, which is updated with data movement. This list allows for ease of maintenance of data without loss of consistency.

Abstract: A mechanism is provided for context based search disambiguation using existing category taxonomy. A client provides additional cues for search term disambiguation through the context of the specific user's browser. A bookmark or favorites data structure is sent along with the search term(s) to be disambiguated. The bookmark data structure acts as pre-existing category taxonomy for a clustering search engine to classify the results of the search. A viewed content history may also be sent along with the search terms to be disambiguated. The viewed content history acts as a cue to a clustering search engine to display as more relevant the results that are classified in the same category as the pages sent along with the search terms.

Abstract: A leakage current monitor circuit provides an accurate statistically representative analog of true off-state leakage current in a digital circuit integrated on a die. At least one N-type transistor and at least one P-type transistor separate from the digital circuit are sized to represent the total area of the corresponding type transistors in the digital circuit. The gates of the N-type transistor and P-type transistors are set to voltages according to the corresponding off-state logic levels of the digital circuit. The N-type and P-type transistors form a portion of corresponding current mirror circuits, which can provide outputs to a leakage current monitor and/or a control circuit such as a comparator that determines when leakage current for the N-type or P-type devices has exceeded a threshold. The output of the measurement/control circuit can be used to determine a temperature of and/or control operation of the digital circuit or the system environment of the integrated circuit.

Abstract: A mechanism is provided that utilizes the attributes of the nodes to build a target list and creates filters based on the node attributes. The filters are installed on the mediators. Each mediator then applies that filter to its own local node list to create a local target list. This local target list will then contain the list of local nodes that need to have a targeted action applied, such as software installed, on them. The mediator then carries out the targeted action, such as software installation, on those nodes. By extending discovered node information with arbitrary attributes, the resolution of target lists defined by filters applied to the master node list is increased.

Abstract: Development tooling receives the extended Web services description language with call flow interactions. The development tooling allows the user to select trivial message exchanges in the call flow. The development tooling may generate servlets for the selected message exchanges automatically to form a template form of the application that will execute in the converged application engine. Alternatively, the development tooling may generate a template form of the application that may be interpreted in an interpretive engine. The user may then drop in higher level business logic. The automatically generated servlets, or template form of the application to be interpreted, are configured to pass to the Web services information, including the last message contents.

Abstract: A mechanism is provided for accessing, by an application running on a first processor, operating system services from an operating system running on a second processor by performing an assisted call. A data plane processor first constructs a parameter area based on the input and output parameters for the function that requires control processor assistance. The current values for the input parameters are copied into the parameter area. An assisted call message is generated based on a combination of a pointer to the parameter area and a specific library function opcode for the library function that is being called. The assisted call message is placed into the processor's stack immediately following a stop-and-signal instruction. The control plane processor is signaled to perform the library function corresponding to the opcode on behalf of the data plane processor by executing a stop and signal instruction.

Abstract: The advanced management module services in a data processing system are configured to determine the system load and provide an input to the early power off warning detection logic that evaluates the power system state to detect a condition when power resources are insufficient to maintain the write caching storage system power within defined acceptable limits. The early power off warning detection logic generates a notification based on the system load and the available power supply resources to maintain maximum availability and reliability characteristics.

Abstract: A mechanism is provided for increasing the scalability of formal verification solutions through enabling the use of input reparameterization on logic models that include memory arrays. A pre-processing mechanism enables the selection of a cut-based design partition which enables optimal reductions though input reparameterization given a netlist with constraints. A post-processing mechanism next prevents input reparameterization from creating topologically inconsistent models in the presence of arrays. Additionally, this technique may be used to rectify inconsistent topologies that may arise when reparameterizing even netlists without arrays, namely false sequential dependencies across initialization constructs. Furthermore, a mechanism is provided to undo the effects of memory array based input reparameterization on verification results.

Abstract: A mechanism is provided for recovering from a data scan error. A service processor determines the nature of the data scan error and, depending on the nature of the error, performs one of a plurality of data scan error recovery procedures.

Abstract: A hardware private array is a thread state storage that is embedded within the processor or within logic associated with a bus or wake-and-go logic. The hardware private array and/or wake-and-go array may have a limited storage area. Therefore, each thread may have an associated priority. If there is insufficient space in the hardware private array, then the wake-and-go mechanism may compare the priority of the thread to the priorities of the threads already stored in the hardware private array and wake-and-go array. If the thread has a higher priority than at least one thread already stored in the hardware private array and wake-and-go array, then the wake-and-go mechanism may remove a lowest priority thread, meaning the thread is removed from hardware private array and wake-and-go array and converted to a flee model.

Abstract: A mechanism is provided for defining and managing virtual discussion threads in a generic synchronous conferencing system. A chat server and chat client define a virtual discussion thread (VDT) entity that includes a group of chat entries or parts of chat entries. The chat entries in a VDT logically belong to the same “hidden” discussion within a chat session. Use of the VDT enables a chat system to support a user in understanding existing discussions by showing VDTs available in the overall list of chat entries and evidencing the chat entries in a VDT.

Abstract: A mechanism for continuously referencing signals over multiple layers in laminate packages provides a continuous path for signals from one layer to another while using the ideal voltage reference for all areas of the package and still avoiding discontinuities in the voltage reference. A reference plane adjustment engine analyzes a package design and identifies an ideal top plane for all areas of the package, including areas under particular chip die(s) and areas that are not under a chip die. The reference plane adjustment engine then modifies the package design to reposition ground planes, source voltage planes, signal planes, and vias between layers to maintain a continuous voltage reference regardless of the top layer. The reference plane adjustment engine provides the resulting mixed voltage plane package design to a design analysis engine. A package fabrication system fabricates the package.

Abstract: An aspect of the present invention improves the accuracy of measuring processor utilization of multi-threaded cores by providing a calibration facility that derives utilization in the context of the overall dynamic operating state of the core by assigning weights to idle threads and assigning weights to run threads, depending on the status of the core. From previous chip designs it has been established in a Simultaneous Multi Thread (SMT) core that not all idle cycles in a hardware thread can be equally converted into useful work. Competition for core resources reduces the conversion efficiency of one thread's idle cycles when any other thread is running on the same core.

Abstract: A mechanism for sharing tasks is provided in which individuals in a share group may signal their intent to complete individual shared tasks and communicate that intent to other individuals in the share group. A required time for completion of the shared tasks may be associated with an individual's signaling of the intent to complete the shared task. The completion of the shared task by the individual signaling intent to complete may be monitored and, if not completed within the associated required time, the performance of the shared task may again be shared with the individuals of the share group. In this way, another individual may signal that individual's intent to perform the shared task and the process may be repeated until the shared task is completed.