Abstract: A coprocessor (14) may be used to perform one or more specialized operations that can be off-loaded from a primary or general purpose processor (12). It is important to allow efficient communication and interfacing between the processor (12) and the coprocessor (14). In one embodiment, a coprocessor (14) generates and provides instructions (200, 220) to an instruction pipe (20) in the processor (12). Because the coprocessor (14) generated instructions are part of the standard instruction set of the processor (12), cache (70) coherency is easy to maintain. Also, circuitry (102) in coprocessor (14) may perform an operation on data while circuitry (106) in coprocessor (14) is concurrently generating processor instructions (200, 220).

Abstract: A circuit is provided wherein a test pulse is provided to a device under test. A module allows the test pulse to pass through to the device under test. The module blocks a reflected pulse from passing through to the device under test when the reflected pulse has an opposite polarity from the polarity of the test pulse. In some cases, the reflected pulse may be detrimental to the device under test if it is not prevented from reaching the device under test. In one embodiment, when a second reflected test pulse is traveling away from the device under test, the module allows the second reflected test pulse to pass through.

Abstract: A semiconductor device is formed on a semiconductor layer. A gate dielectric layer is formed over the semiconductor layer. A layer of gate material is formed over the gate dielectric layer. The layer of gate material is patterned to form a gate structure. Using the gate structure as a mask, an implant into the semiconductor layer is performed. To form a first patterned gate structure and a trench in the semiconductor layer surrounding a first portion and a second portion of the semiconductor layer and the gate, an etch through the gate structure and the semiconductor layer is performed. The trench is filled with insulating material.

Abstract: A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.

Abstract: A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.

Abstract: A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.

Abstract: Timing circuitry may use control circuitry to control calibration circuitry to calibrate a counter so that an adder and a calibration period counter are not required. Concatenation circuitry may be used to concatenate a portion of the counter value and the calibration value to provide a calibrated value to the counter. The results from match circuitry may be used to provide status and control information to a calibration history bit and to an enable circuit. The counter may be an up counter or a down counter.

Abstract: A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.

Abstract: A device (12) may have a pressure sensitive portion (17) which is protected from corrosion by a pressure transmitting material (20). Pressure transmitting material (20) may also be used to transmit pressure to pressure sensitive portion (17). A masking material (22) may be used to define an opening (26) in encapsulating material (24).

Abstract: A data processing system has an interrupt controller which provides an interrupt request along with a corresponding interrupt identifier and a corresponding interrupt vector to a processor. If the processor accepts the interrupt, the processor returns the same interrupt identifier value by way of interrupt identifier, along with interrupt acknowledge, to the interrupt controller. An interrupt taken/not taken indicator may also be provided. The communications interface used to coordinate interrupt processing between the interrupt controller and the processor may be asynchronous.

Abstract: A MEMS device uses both piezoelectric actuation and electrostatic actuation and also provides enough electrostatic force to enable very low voltage operation. As the electrostatic actuation uses DC and the piezoelectric actuation uses high frequency, the structure of the device minimizes the coupling of the two actuator structures to reduce noise. In addition, for some embodiments, the location of the physical structures of the piezoelectric actuator and electrostatic actuator generates higher contact force with lower voltage. For some embodiments, the piezoelectric actuator and electrostatic actuator of the device are connected at the contact shorting bar or capacitor plate location. This makes the contact shorting bar or capacitor plate the focal point of the forces generated by all of the actuators, thereby increasing the switch contact force.

Abstract: An integrated circuit has a plurality of terminals for making electrical connection to the integrated circuit. At least one device is formed adjacent an outer edge of the integrated circuit. The device includes at least one metal conductor for forming an edge seal for protecting the integrated circuit during die singulation. The device is coupled to one or more functional circuits within the integrated circuit by routing the at least one metal conductor to the one or more functional circuits, the at least one device providing a reactance value to the one or more functional circuits for non-test operational use. The device may be formed as one or more capacitors or as one or more inductors. Various structures may be used for the capacitor and the inductor.

Abstract: A pad (20) is electrically connected to a first I/O cell (14) while also physically overlying active circuitry of a second I/O cell (16). Note that although the pad (20) overlies the second I/O cell (16), the pad (20) is not electrically connected to the I/O cell (16). Such a pattern may be replicated in any desired manner so that the I/O cells (e.g. 300-310) may have a finer pitch than the corresponding pads (320-324 and 330-335). In addition, the size of the pads may be increased (e.g. pad 131 may be bigger than pad 130) while the width “c” of the I/O cells (132-135) does not have to be increased. Such a pattern (e.g. 500) may be arranged so that the area required in one or more dimensions may be minimized.

Abstract: A circuit can provide an approximately constant resistance value that is virtually independent of process and temperature variations. A current control circuit may use a device that tracks the changes in a corresponding device over process and temperature variations. As a result, the behavior of device may be used to help determine the control information provided to device in order to maintain an approximately constant resistance Rm over process and temperature variations. The approximately constant resistance Rm may be used to provide an approximately constant current ILED. A wide variety of applications, not just LED drivers, may benefit from the use of an approximately constant resistance and/or current.

Abstract: New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry (402, 417, 480) may be used to provide steering for additional signals such as interrupts. Other shared resources (24, 30) may use more centralized circuitry (36) to perform a steering function for additional signals.

Abstract: A detect circuit may be used to detect one or more characteristics corresponding to the fuse being programmed. When the one or more characteristics of the fuse being programmed reach the desired states or values, the programming of the fuse is discontinued. Thus, the programming duration for each fuse is customized for each fuse. As a result, for some embodiments, there may be fewer fuses that have been over-programmed. In addition, for some embodiments, the range of impedances of the programmed fuses have a narrower distribution of impedances due to the use of the detect circuit.

Abstract: Circuitry on integrated circuits usually includes protection against electrostatic discharge (ESD) events. A second ESD current path may be provided in addition to a first ESD current path for shunting ESD current away from circuitry to be protected during an ESD event. In addition to the standard power and ground buses used to provide power and ground voltages to the protected circuitry, one or more extra power and/or ground buses and associated circuitry may be added for improved ESD protection.

Abstract: A test apparatus and device under test has a probe that can be located very close to contact pads and that requires very few solder connections. In addition, the probe can be configured to meet any appropriate and desired electrical specification while still using a same circuit board. There is no need to attach discrete components to a circuit board. Thus, by using a configurable probe, a single circuit board may be used with multiple probes or a reconfigurable probe to test for compliance with a variety of different electrical specifications having different requirements.

Abstract: A memory having at least one memory array block, the at least one memory array block comprising N wordlines, wherein N is greater than one, is provided. The memory comprises a plurality of sense amplifiers coupled to the at least one memory array block. The memory further comprises at least one dummy bitline, wherein the at least one dummy bitline comprises M dummy bitcells, wherein M is equal to N. The memory further comprises a timing circuit coupled to the at least one dummy bitline, wherein the timing circuit comprises at least one stack of pull-down transistors coupled to a sense circuit for generating a latch control output signal used for timing control of memory accesses. Timing control may include generating a sense trigger signal to enable the plurality of sense amplifiers for read operations and/or generating a local reset signal for terminating memory accesses, such as disabling the plurality of write drivers for write operations.

Abstract: In one embodiment of the present invention an interpreted language, such as, for example, Java, is selectively optimized by partitioning the interpreted language code (98) into a plurality of blocks (80-83) based on the complexity of each of the interpreted language instructions. In one embodiment of the present invention, each of the plurality of blocks is identified as either a block to be compiled into native code (80-82) if the block is simple, or a block to be interpreted (83) if the block is complex. The compiled and interpreted blocks are appended to form in-line mixed code (99) that contains both native code (90-92) and interpreted language code (93). This mixed code is formed before run-time, so that no further compilation is required at run-time. A processing unit (102) may be used to execute the native code directly without the use of a Java VM (10), while also executing, in-line, the interpreted language code (93) which requires use of the Java VM (10) to interpret the Java bytecodes.