Abstract: Embodiments of the present invention relate generally to receivers. One embodiment relates to a digital FM receiver having multiple sensors (e.g. antennas). In one embodiment, the digital receiver includes a baseband unit having a channel processing unit. In one embodiment, the channel processing unit is capable of calculating or estimating a phase difference between the incoming signals prior to combining them. One embodiment uses phase estimation method for diversity combining the signals while another embodiment utlizes a hybrid phase lock loop method. Also, some embodiments of the present invention provide for echo-cancelling after diversity combining. An alternate embodiment of the channel processing unit utilizes a space-time unit to diversity combine and provide echo cancelling for the incoming signals.

Abstract: An optical device uses one or more doped pockets in one embodiment to increase the electric field at one or more edges of the light absorbing region to increase the efficiency of the optical device. In alternate embodiments, the optical device uses an overlying light-barrier layer to reduce optical absorption within the more highly doped region. Some embodiments use a comb-like structure for the optical device to reduce capacitance and create a planar CMOS compatible structure.

Abstract: Embodiments of the present invention relate generally to receivers. One embodiment relates to a digital FM receiver having multiple sensors (e.g. antennas). In one embodiment, the digital receiver includes a baseband unit having a channel processing unit. In one embodiment, the channel processing unit is capable of calculating or estimating a phase difference between the incoming signals prior to combining them. One embodiment uses phase estimation method for diversity combining the signals while another embodiment utlizes a hybrid phase lock loop method. Also, some embodiments of the present invention provide for echo-cancelling after diversity combining. An alternate embodiment of the channel processing unit utilizes a space-time unit to diversity combine and provide echo cancelling for the incoming signals.

Abstract: A vehicular audio system receives audio inputs from audio sources and a radio receiver. Analog audio is converted to digital, and digital audio remains natural digital. The receiver front end converts a radio signal to an intermediate frequency then an ADC converts that to a digital signal. The inputs that are converted to digital are selectively mixed with each other and with the natural digital signals. This allows for sounds from multiple sources to be heard simultaneously so that a telephone ring may be provided without requiring background music to be interrupted and for uses such as voice by microphone over a music tape. A reference frequency to the receiver front end of 7.2 MHz is particularly beneficial for noise reduction and consequent mixing of digital audio at 48 KHz, the standard frequency for typical digital audio inputs.

Abstract: A variable length decoder (200) detects the class of a codeword in a bit stream (332). If the codeword is first class, a first set of encoding rules are used to generate a pointer “C A B” into a table to retrieve table content (250), where the values of “C”, “A”, and “B” are determined from the codeword. If the codeword is second class, a second set of encoding rules are used to generate a pointer “0 (C+X) Z” into a table to retrieve table contents (252), where the values of “C” and “Z” are determined from the codeword and the value of “X” is a predetermined value. The code length of each codeword is calculated while the pointer is being generated, and thus the code length does not have to be stored in memory (204).

Abstract: Embodiments of the present invention deal generally with circuitry and methods for converting a sampled digital signal (32) to a naturally sampled digital signal (34). One embodiment relating to a method includes receiving the sampled digital signal, calculating a duty ratio estimate (33) using feedback (52), and using interpolation (62) to determine the naturally sampled digital signal. Circuitry for converting a sampled digital signal (32) to a naturally sampled digital signal (34) includes a natural sampler, where the natural sampler includes an input to receive the sampled digital signal (32) and an input to receive a feedback signal (52). The natural sampler has an output to provide the naturally sampled digital signal (34). In one embodiment, the natural sampler calculates a duty ratio (33) using the feedback signal (52) and uses interpolation to determine the naturally sampled digital signal (34).

Abstract: A data processing system (400) is configured when coming out of reset using memories of various bit widths (440, 450, 460). The bytes that make up the reset vector (300) are fetched individually through separate memory operations from the memory that stores the reset vector. These bytes are stored in a pre-determined manner within each of the potential memory structures (440, 450, 460) such that predetermined addresses will retrieve the different bytes on the same portion of the data bus. A configuration value (310) portion of the reset vector (300) retrieved may be used to configure various parameters (352-356, 362) within the data processing system (400) such that parameters related to the memory or other functional characteristics of the system are initialized. The configuration value (310) may include data and control sections such that the control section determines how the data section of the configuration value (310) is applied to various parameters within the data processing system (400).

Abstract: A method and apparatus for a pulse width modulated (PWM) signal (30, 130) is provided. The input is a digital signal which is a modulated signal (24, 124). In the illustrated form, the modulated input signal is either a PDM signal or a PCM signal. In one embodiment of the present invention a PCM to PWM converter (16, 116) includes correction of duty ratio circuitry (48). The methodology used may include recursion on the values obtained after prediction, interpolation, and correction. The digital to analog conversion system (10) uses a PDM to PWM converter (20) which operates in an all digital domain and includes no analog circuitry.

Abstract: A processor (12) uses an architecture having a plurality of redundant state machines (86, 90) and a new instruction format (30) to increase efficiency of the utilization of operational circuitry, such as a multiply accumulate unit MAC (52). Thus the processor (12) can switch contexts or channels without incurring any dead or wasted cycles for the MAC unit (52).

Abstract: A processor (12) to coprocessor (14) interface supporting multiple coprocessors (14, 16) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (12) and coprocessor (14) on a bi-directional shared bus (28) either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus (28) is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.

Abstract: Method and apparatus for performing access censorship in a data processing system (10). In one embodiment, a digital data processing system (10) has a sub-system (34) that can be protected against intrusions, yet is still accessible and/or alterable under certain defined conditions. In a non-volatile storage portion (48) of the data processing system (10), censorship information is stored to enable an access control mechanism. Access control information (42) to selectively disable the access control mechanism is programmably generated. Additional access control information (44) can be employed to reprogram a data processing system (10) containing access protected data in a secure mode.

Abstract: Buffering circuitry (10) uses pull-up slew rate control circuitry (12) and pull-down slew rate control circuitry (14) to control the rising and falling slew rates of an output signal (50) provided by buffering circuitry (10). Pull-up slew rate control circuitry (12) and pull-down slew rate control circuitry (14) may be used in an embodiment of buffering circuitry (10) which provides a higher output voltage VHIGH than the standard power voltage VPOWER which is used to power most of the circuitry. Buffering circuitry (10) utilizes distributed resistive elements (89-91) to provide improved electrostatic discharge protection. Buffering circuitry (10) utilizes a low power level shifter (16). Voltage reference generation circuitry (18) may be used to provide a stable low power reference voltage VREF (42).

Abstract: A data processing system (10) has a multifield register (62) which has two fields, a selection field (90) and an information field (91). The selection field (90) identifies the source of the information loaded in the information field (91). In one embodiment, the multifield register (62) is an interrupt flag register (62) and the selection field (90) identifies which of the two registers portions (59,60) of the interrupt pending register (58) is loaded into the multifield register (62). The low register portion (59) can identify up to thirty-one sources of interrupt requests and the high register portion (60) can identify up to thirty-two sources of interrupt requests even though the information field (91) is only thirty-one bits. This is achievable because the selection field (90) may serves a dual function, namely as a flag bit and as bit-32 of the interrupt pending register (58).

Abstract: A method and apparatus for assigning unique addresses to each generic “node” in a distributed control system that contains a main controller (52) coupled to a plurality of generic nodes (54) via a distributed communication bus (55). The main controller (52) provides currents and/or voltages to the communication bus (55) via a supply (58). In one embodiment, each node (54) processes the current and voltages to store reference voltages and distance voltages proportional to its distance along the communication bus (55). In another embodiment, each node (54) signals to the main controller (52) when the distance voltage reaches a certain value relative to the reference voltage. The main controller (52) processes the arrival times of these signals to determine a relative distance to each node (54). This distance information is used to assign a unique address to each generic node (54) for identification during normal mode of operation.

Abstract: A memory has sense amplifiers that provide data onto a global data lines that are received by secondary amplifiers. The sense amplifiers and the secondary amplifiers are enabled by clocks that are timed by programmable delay circuits. The programmable delays are programmed by delay selection circuits that provide a continuous output to the programmable delay circuits. There are two delay selection circuits. One is shared by all of the programmable delay circuits that enable the sense amplifiers, and one is shared by all of the programmable delay circuits that enable the secondary amplifiers. The outputs of these two delay selection circuits are chosen to provide the output which programs the programmable delay circuits for optimizing the worst case of the access time of the memory.

Abstract: In one embodiment, an integrated circuit (10, 110) has a contention detection circuit (12, 112) coupled to a tri-stateable output buffer (18, 118). The contention detection circuit (12, 112) provides a contention tri-state control signal (34, 134) to the tri-stateable output buffer (18, 118) in order to place it in a tri-stated condition when an external device (31, 131), such as a computer, supplies power to an input/output pad (22, 122) on the integrated circuit (10, 110). Thus, external and/or internal buffer contention is avoided when an external device (31, 131), such as a computer, supplies power to an input/output pad (22, 122) on the integrated circuit (10, 110).

Abstract: A method and apparatus for processing multi-cycle instructions. In one embodiment, the method includes beginning execution of a multi-cycle instruction by the processing device, and, during execution of the multi-cycle instruction, comparing a threshold value to a count value that indicates a number of remaining cycles before completion of the multi-cycle instruction. In one embodiment, the apparatus includes a processing unit. The processing unit includes an interrupt control module that has an interrupt request signal input and a second input to receive a multi-cycle instruction interrupt signal. The multi-cycle instruction interrupt signal is to indicate an interruptible interval when an interrupt of a multi-cycle instruction is permitted prior to completion of the multi-cycle instruction.

Abstract: A processor (12) to coprocessor (14) interface supporting multiple coprocessors (14, 16) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (12) and coprocessor (14) on a bi-directional shared bus (28) either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus (28) is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.

Abstract: A method and apparatus affects subsequent instruction processing in a data processor (10). In one embodiment, a delay interrupt recognition instruction (IDLY4) is executed by data processor (10) to delay or conditionally delay interrupt recognition for a controlled interval, either for a predetermined period of time or for a predetermined number of instructions, so that a read/modify/write sequence of instructions can be performed without dedicated instructions which define the modification operation. The IDLY4 instruction may affect the manner in which subsequent instructions affect a condition bit (38). The condition bit (38) may thus be used to determine if exception processing occurred during the interrupt non-recognition interval after execution of the IDLY4 instruction.

Abstract: In one embodiment, a development interface (14) for a data processor (10) includes development registers (39), auxiliary pin interface and control (32), auxiliary pins (31), and a JTAG controller (4)).