Abstract: New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry (402, 417, 480) may be used to provide steering for additional signals such as interrupts. Other shared resources (24, 30) may use more centralized circuitry (36) to perform a steering function for additional signals.

Abstract: A semiconductor device includes a memory array having a plurality of non-volatile memory cells. Each non-volatile memory cell of the plurality of non-volatile memory cells has a gate stack. The gate stack includes a control gate and a discrete charge storage layer such as a floating gate. A dummy stack ring is formed around the memory array. An insulating layer is formed over the memory array. The dummy stack ring has a composition and height substantially the same as a composition and height of the gate stack to insure that a CMP of the insulating layer is uniform across the memory array.

Abstract: An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control electrode or gate formed of a single conductive layer of material. A second region of the integrated circuit has a plurality of memory cells, each having a control electrode of at least two conductive layers of material that are positioned one overlying another. The at least two conductive layers are at substantially a same electrical potential when operational and form a single gate electrode. In one form each memory cell gate has two polysilicon layers overlying a nanocluster storage layer.

Abstract: Storage circuitry (66) may be used to store the values of fuses (77) so that storage circuitry (66) can be read instead of fuses (77). By accessing the fuse values from storage circuitry (66) rather than from fuses (77), there will be no sense current to fuses (77) that may cause marginal fuse blowage for fuses that have not yet been blown. This helps to prevent the situation in which an unblown fuse is erroneously read as having been blown. The use of storage circuitry (66) thus significantly improves the reliability of fuse module (20). For some embodiments, selection storage circuitry (64) may be used to determine whether storage circuitry (66) may be read or whether one of fuses (77) must be read in order to retrieve the desired current fuse value. The fuse value stored in storage circuitry (66) can also be used as direct hardware signals (80).

Abstract: A circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). At least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device (115) may be placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). The conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126, 326) may be electrically conductive or electrically non-conductive.

Abstract: A reciprocal design symmetry allows stacked wafers or die on wafer to use identical designs or designs that vary only by a few layers (e.g. metal interconnect layers). Flipping or rotating one die or wafer allows the stacked die to have a reciprocal orientation with respect to each other which may be used to decrease the interconnect required between the vertically stacked die and or wafers. Flipping and/or rotating may also be used to improve heat dissipation when wafer and/or die are stacked. The stacked wafers or die may then be packaged.

Abstract: One use for delay adjustment circuit (32), coarse-grain delay offset circuit (34), and fine-grain delay synthesis circuit (36) may be as part of a delay replication circuit (30) used to replicate the frequency versus voltage behavior of an integrated circuit (29). Also, a circuit (30) and method for determining optimal power and frequency metrics of integrated circuit (29) is also described. In addition, a method for determining programmable coefficients to replicate frequency and supply voltage correlation is described.

Abstract: Storage circuits (180-183 and 280-281) may be used for low power operation while allowing fast read access. In one embodiment (e.g. circuit 100), shared complementary write bit lines (101, 102), separate read bit lines (103-106), a shared read word line (107), and separate write word lines (108-111) are used. In an alternate embodiment (e.g. circuit 200), shared complementary write bit lines (201, 202), a shared read bit line (203), separate read word lines (206-207), and separate write word lines (208-209) are used. The storage circuit may be used in a variety of contexts, such as, for example, a register file (17), a branch unit (15), an SRAM (19), other modules (20), a cache (18), a buffer (21), and/or a memory (14).

Abstract: A non-volatile memory (NVM) that can be optimized for data retention or endurance is divided into portions that are optimized for one or the other or potentially some other storage characteristic. For the portion allotted for data retention, the memory cells are erased to a relatively greater extent. For the portion allotted for high endurance, the memory cells are erased to a relatively lesser extent. This is conveniently achieved by simply raising the level of the current reference that is used to determine if a cell has been sufficiently erased for the high data retention cells. The higher endurance cells thus will typically receive fewer erase pulses than the memory cells for high data retention. The reduced erasing requirement for the high endurance cells results in overall faster erasing and less stress on the high endurance cells as well as on the circuitry that generates the high erase voltages.

Abstract: An EUV mask (10, 309) includes an opening (26) that helps to attenuate and phase shift extreme ultraviolet radiation using a subtractive rather than additive method. A first embedded layer (20) and a second embedded layer (21) may be provided between a lower multilayer reflective stack (14) and an upper multilayer reflective stack (22) to ensure an appropriate and accurate depth of the opening (26), while allowing for defect inspection of the EUV mask (10, 309) and optional defect repair. An optional ARC layer (400) may be deposited in region (28) to reduce the amount of reflection within dark region (28). Alternately, a single embedded layer of hafnium oxide, zirconium oxide, tantalum silicon oxide, tantalum oxide, or the like, may be used in place of embedded layers (20, 21). Optimal thicknesses and locations of the various layers are described.

Abstract: Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried layers. Any one or more of these methods may be used in combination. Mechanical stress control may be useful in the channel region of a semiconductor device to maximize its performance. In addition, these same techniques and structures may be used for other purposes besides mechanical stress control.

Abstract: The invention relates to an integrated circuit (IC), and more particularly to security to protect an IC (10) against unauthorized accesses. In one embodiment, an identifier is provided external to IC 10. A corresponding input IC security key (52) is then provided to IC 10 and compared to a stored IC security key (30). If the input IC security key (52) and the stored IC security key (30) do not match, access to protected functional circuitry (12) is prohibited. The present invention may use any debug interface, including standard debug interfaces using the JTAG 1149.1 interface defined by the IEEE.

Abstract: The invention relates to debug circuitry (20) and more particularly to a method and apparatus for providing security for debug circuitry (20). In one embodiment, a plurality of non-volatile elements (38) are used in providing selective disabling and re-enabling of at least a portion of the debug circuitry (20). Authentication may also be used. The present invention may use any debug interface, including standard debug interfaces such as the JTAG debug interface defined by the IEEE.

Abstract: A semiconductor device (10) having a gate (16, 18 or 16, 18, 26, 28) with a thin conductive layer (18) is described. As the physical dimensions of semiconductor devices are scaled below the sub-micron regime, very thin gate dielectrics (16) are used. One problem encountered with very thin gate dielectrics is that the carriers can tunnel through the gate dielectric material, thus increasing the undesirable leakage current in the device. By using a thin layer for conductive layer (18), quantum confinement of carriers within conductive layer (18) can be induced. This quantum confinement removes modes which are propagating in the direction normal to the interfacial plane 15 from the Fermi level. Thus, the undesirable leakage current in the device (10) can be reduced. Additional conductive layers (e.g. 28) may be used to provide more carriers.

Abstract: Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried layers. Any one or more of these methods may be used in combination. Mechanical stress control may be useful in the channel region of a semiconductor device to maximize its performance. In addition, these same techniques and structures may be used for other purposes besides mechanical stress control.

Abstract: An automated process for designing a memory having row/column replacement is provided. In one embodiment, a potential solution array (50) is used in conjunction with the row/column locations of memory cell failures to determine values stored in the actual solution storage circuitry (92). A selected one of these vectors stored in the actual solution storage circuitry (92) is then used to determine rows and columns in memory array (20) to be replaced with redundant rows (22, 24) and redundant columns (26).

Abstract: In one embodiment, an integrated circuit which uses one or more re-useable modules may use a signature generated by a duplicate state machine or an unmodified state machine to select, control, or otherwise affect a resource on the integrated circuit, where affecting the resource was not part of the original design and state diagram of the unmodified state machine. In one embodiment, a method and apparatus is provided for dynamically reconfiguring a plurality of test circuits in re-useable modules on an IC without modifying the controller state machine in the re-usable module.

Abstract: A read allocation indicator (e.g. read allocation signal 30) is provided to storage circuitry (e.g. cache 22) to selectively determine whether read allocation will be performed for the read access. Read allocation may include modification of the information content of the cache (22) and/or modification of the read replacement algorithm state implemented by the read allocation circuitry (70) in cache (22). For certain types of debug operations, it may be very useful to provide a read allocation indicator that ensures that no unwanted modification are made to the storage circuitry during a read access. Yet other types of debug operations may want the storage circuitry to be modified in the standard manner when a read access occurs.

Abstract: A method and apparatus for entering a low power mode is provided. In one embodiment, data processing system (10) has power control circuitry (52) which may be used to control power usage in data processing system (10). Power mode select circuitry (84) may be used to select a power mode. Depending upon the power mode selected, power control circuitry (52) may use a cascaded approach to selecting which portions of data processing system (10) will be powered down, and thus how deeply data processing system (10) will be powered down.

Abstract: One use for delay adjustment circuit (32), coarse-grain delay offset circuit (34), and fine-grain delay synthesis circuit (36) may be as part of a delay replication circuit (30) used to replicate the frequency versus voltage behavior of an integrated circuit (29). Also, a circuit (30) and method for determining optimal power and frequency metrics of integrated circuit (29) is also described. In addition, a method for determining programmable coefficients to replicate frequency and supply voltage correlation is described.