Patents Assigned to Agere Systems Inc.
  • Patent number: 8275151
    Abstract: An improved speakerphone for a cellular telephone, portable telephone handset, or the like. In one embodiment, a receiver provides an audio signal, and a first phase-shifter phase-shifts the audio signal by a first phase-shift amount. A second phase-shifter phase-shifts the audio signal by a second phase-shift amount and drives a loudspeaker. A processor sets the first phase-shift amount to each one of a plurality of phase-shift amounts and determines a corresponding average-to-peak ratio value of the first phase-shifted audio signal. The processor then selects one of the plurality of phase-shift amounts having a corresponding average-to-peak ratio value that meets at least one criteria (e.g., the largest one of the average-to-peak ratio values), and then sets the second phase-shift amount to be the same as the selected phase-shift amount. This enhances the perceived loudness of sound from loudspeaker.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: September 25, 2012
    Assignee: Agere Systems Inc.
    Inventor: Marcello Caramma
  • Publication number: 20120239719
    Abstract: Embodiments of the present invention generate a normalized floating-point sum from at least two floating-point addends. The mantissa of an un-normalized floating-point sum is generated. A pointer is generated which indicates the location of the left-most significant digit (LSD) in the mantissa of the un-normalized floating-point sum. A plurality of possible values for the exponent of the normalized floating-point sum are generated, in parallel with each other and in parallel with the mantissa addition, based on a common exponent value (e.g., the largest of the two addends' exponent values). Based on the LSD pointer, one of the possible values is selected as the exponent of the normalized floating-point sum. The mantissa of the un-normalized floating-point sum is normalized to yield the mantissa of the normalized floating-point sum. By generating the possible exponent values in parallel, embodiments of the present invention can result in significant time savings over prior-art methods.
    Type: Application
    Filed: June 4, 2012
    Publication date: September 20, 2012
    Applicant: AGERE SYSTEMS INC.
    Inventor: Lawrence A. Rigge
  • Publication number: 20120238327
    Abstract: In one embodiment, a mobile station including a chassis having a display, a power reducer, a proximity sensor, and a microprocessor. The power reducer controls power consumption of the display. The proximity sensor is coupled to the chassis and causes the power consumption to be reduced when the display is within a predetermined range of an external object. The microprocessor is coupled to the proximity sensor and to the display and automatically activates the proximity sensor based on the mobile station receiving an incoming wireless telephone call.
    Type: Application
    Filed: May 16, 2012
    Publication date: September 20, 2012
    Applicant: Agere Systems Inc.
    Inventors: Norman Goris, Wolfgang Scheit
  • Patent number: 8271847
    Abstract: Methods and apparatus are provided for N+1 packet level mesh protection. An error correction encoding method is provided that assembles M-T data packets; appends a sequence number and a payload integrity check to each of the M-T data packets; and creates T protection packets having the sequence number and payload integrity check, wherein a payload for each of the T protection packets are formed from corresponding symbols in the M-T data packets. An error correction decoding method is also provided that receives a plurality of error-free packets and one or more packets having an error; and reconstructs the one or more packets having an error by applying block erasure decoding to said plurality of error-free packets, whereby one packet having an error can be reconstructed for each protection packet used to encode the received packets.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: September 18, 2012
    Assignee: Agere Systems Inc.
    Inventor: Paul Langner
  • Patent number: 8270502
    Abstract: In one embodiment, a demodulator demodulates a multi-carrier modulated signal having two pilot tones. The demodulator calculates a first phase angle for the first pilot tone and a second phase angle for the second pilot tone based on the time-domain multi-carrier modulated signal. A timing-frequency offset estimate is calculated using the first and second phase angles. Further, a fine carrier-frequency offset estimate is calculated for each pilot tone based on the corresponding phase angle and the timing-frequency offset estimate. Each fine carrier-frequency offset estimate is combined with a coarse estimate and weighted. The weighted estimates are then combined. In further embodiments, the timing-frequency offset estimate is weighted and combined with a weighted timing-frequency offset estimate generated using a cyclic prefix. In yet further embodiments, the weighted carrier-frequency offset estimates are combined with a weighted carrier-frequency offset estimate generated using a cyclic prefix.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: September 18, 2012
    Assignee: Agere Systems Inc.
    Inventor: Yhean-Sen Lai
  • Patent number: 8262289
    Abstract: A reversible fastener is provided for a resealable bag-type container (100) having first and second opposing wall panels (102,104), each of the first and second opposing wall panels having an interior face and an exterior face. The fastener includes first and second closure mechanisms. The first closure mechanism (114) includes first and second complementary interlockable components (116,118) disposed on the interior face of each of the first and second opposing wall panels proximate a top periphery (112) of the first and second opposing wall panels. The second closure mechanism (120) includes first and second complementary interlockable components (122,124) disposed on the exterior face of each of the first and second opposing wall panels proximate a top periphery of the first and second opposing wall panels.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: September 11, 2012
    Assignee: Agere Systems Inc.
    Inventors: Roger A. Fratti, Cathy Lynn Hollien
  • Publication number: 20120225689
    Abstract: A cordless telephone which allows a user to play MP3 digital audio bit stream music, using the remote handset of a cordless telephone to control the functions of the MP3 player. The cordless telephone remains usable as a typical cordless telephone with all the features and conveniences of a cordless telephone including, but not limited to, connection of a telephone call between a calling party and a called party, caller ID information, voice messaging features, etc. MP3 digital audio bit stream music may be downloaded from a remote source through, e.g., the Internet and a PC.
    Type: Application
    Filed: May 16, 2012
    Publication date: September 6, 2012
    Applicant: Agere Systems Inc.
    Inventors: Qinghong Cao, Liang Jin, Wenzhe Luo, Jian Wu, Zhigang Ma
  • Patent number: 8261241
    Abstract: In one embodiment, a method for correlating log entries in a log file to the line numbers of formatted-string output functions in source code, where the formatted-string output functions contain instructions to generate the log entries in the log file. The method includes locating the formatted-string output functions in the source code, where each formatted-string output function contains a format string. Each format string is processed to generate a corresponding regular expression to match log entries outputted by the corresponding formatted-string output function. Each regular expression is associated with the line number of the corresponding formatted-string output function. The resultant list of regular expressions and corresponding line numbers is processed with the log file, where log entries in the log file are modified to indicate the line numbers associated with matching regular expressions.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: September 4, 2012
    Assignee: Agere Systems Inc.
    Inventors: Francisco Gutierrez, Assaf Landschaft, Salai Valarmathi Ramakrishnan, Michael Sprenglewski
  • Patent number: 8261022
    Abstract: A method and apparatus are disclosed for locking the most recently accessed frames in a cache memory. The most recently accessed frames in a cache memory are likely to be accessed by a task again in the near future. The most recently used frames may be locked at the beginning of a task switch or interrupt to improve the performance of the cache. The list of most recently used frames is updated as a task executes and may be embodied, for example, as a list of frames addresses or a flag associated with each frame. The list of most recently used frames may be separately maintained for each task if multiple tasks may interrupt each other. An adaptive frame unlocking mechanism is also disclosed that automatically unlocks frames that may cause a significant performance degradation for a task. The adaptive frame unlocking mechanism monitors a number of times a task experiences a frame miss and unlocks a given frame if the number of frame misses exceeds a predefined threshold.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: September 4, 2012
    Assignee: Agere Systems Inc.
    Inventors: Harry Dwyer, John Susantha Fernando
  • Patent number: 8260240
    Abstract: An automatic gain control (AGC) for use in a digital radio receiver that allows at least two types of input signal to be processed using a single receiver front end by supporting two modes of operation, each optimized for one particular signal type, and a third mode not optimized for either. The AGC enables smooth switching between the optimized modes of operation via the non-optimized mode. By measuring a difference in the strength between the demodulated signals, and comparing that to two preset values, the AGC controls which mode of operation to place the receiver in. Modes of operation are maintained by adjusting the gain of a variable gain amplifier (VGA), so that an appropriate incoming signal is amplified to a level that is suitable for an analogue-to-digital (ADC) converter. The AGC is compatible with existing satellite digital audio radio system (SDARS) transmission capabilities.
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: September 4, 2012
    Assignee: Agere Systems Inc.
    Inventors: Robert Malkemes, Denis Orlando, Jie Song, Eric Zhong
  • Patent number: 8260323
    Abstract: A tracking/locating/paging system utilizes a “pre-established” local area network to determine essentially real-time information regarding one or more client devices within a closed communication environment (“pre-established” also considered as including an ad hoc network connection of devices deployed to serve a common interest). Particularly suited for arrangements such as an amusement park, college campus, shopping mall, etc., the service of the present invention utilizes conventional client devices and includes the ability to transmit an identification signal unique to each device. Various network access points distributed through the closed environment receive these unique identification signals and can therefore pinpoint the location of various client devices in real time. Accordingly, a paging function may be added to further enhance the communication aspects of the tracking and locating features of the present invention.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: September 4, 2012
    Assignee: Agere Systems Inc.
    Inventors: Peter Eyolf Bronner, Dwight David Daugherty, Roger A. Fratti
  • Publication number: 20120218986
    Abstract: In a packet-based (e.g., Ethernet) network, such as the network of central offices and base stations of a wireless telephone system, a node receives one or more incoming packet-based signals from one or more other nodes of the network and recovers a clock signal from each incoming packet-based signal. The node selects one of the recovered clock signals as the node's reference clock signal. When the node is part of a base station, the node uses the selected clock to generate and transmit one or more outgoing packet-based signals to one or more central offices. The node also uses the selected clock to generate the base station's wireless transmissions. In one implementation, the base stations and central offices are connected by Ethernet facilities.
    Type: Application
    Filed: May 3, 2012
    Publication date: August 30, 2012
    Applicant: AGERE SYSTEMS INC.
    Inventor: P. Stephan Bedrosian
  • Patent number: 8254049
    Abstract: Various embodiments of the present invention provide systems and methods for synchronizing data processing. As one example, a method for synchronizing data processing is disclosed that includes receiving a data input, and sampling the data input at a sample period to generate a sample set. A first pattern is received and a first periodic boundary associated with the first pattern is identified. In one particular case, the first pattern is a preamble pattern included as sector data on a storage medium, and the first periodic boundary is a 4T boundary. Further, a second pattern is detected in the sample that is used to establish a second periodic boundary. In one particular case, the second pattern is a SAM pattern included as sector data on a storage medium, and the second periodic boundary is a 1T boundary. Based at least in part on the first periodic boundary and the second periodic boundary, a time to transmit or assert a data-found signal is determined.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: August 28, 2012
    Assignee: Agere Systems Inc.
    Inventor: Viswanath Annampedu
  • Patent number: 8254267
    Abstract: A traffic generator generates a plurality of traffic flows, with each of the traffic flows being associatable with one or more of a plurality of output interfaces of the traffic generator. In an illustrative embodiment, each of the output interfaces may have any desired combination of the traffic flows associated therewith. The traffic flows may be generated based on user selection of at least one of a protocol encapsulation, a packet size distribution model, a packet arrival time distribution model, a traffic model, and a packet payload description. Information characterizing one or more of the traffic flows may be stored as a traffic file in a memory associated with the traffic generator.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: August 28, 2012
    Assignee: Agere Systems Inc.
    Inventors: D Srivatsan, Vinoj N. Kumar, Kaushik Nath, Srinivasan Rangarajan, Chandramouleeswaran Sankaran
  • Patent number: 8255199
    Abstract: In one embodiment of the present invention, the performance of an electronic circuit having a clock path between a clock source cell and a clock leaf cell is characterized over a simulation duration, where the clock path has one or more intermediate cells. Variations in the effective power supply voltage level least one intermediate cell over the simulation duration are determined using a system-level power-grid simulation tool. Static timing analysis (STA) software is used to determine cell delays for at least one of the intermediate cells for different clock-signal transitions at different times during the simulation duration. The cell delays are then used to generate one or more metrics characterizing the performance of the electronic circuit, such as maximum and minimum pulse widths, maximum cycle-to-cycle jitter, and maximum periodic jitter.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: August 28, 2012
    Assignee: Agere Systems Inc.
    Inventor: Hyuk-Jong Yi
  • Patent number: 8250386
    Abstract: A processor circuit having reduced power consumption includes an analog front end operative to receive an analog signal supplied to the processor circuit and to generate a digital signal indicative of the analog signal. The processor further includes a digital back end operative to generate a digital output signal as a function of the digital signal generated by the analog front end. A buffer is coupled between the analog front end and the digital back end. In a first mode of operation, the digital back end operates at a substantially same data rate as the analog front end and the buffer is bypassed. In a second mode of operation, the digital back end operates at a higher data rate than the analog front end and the buffer is used to store outputs of the analog front end.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: August 21, 2012
    Assignee: Agere Systems Inc.
    Inventor: Nils Graef
  • Patent number: 8250438
    Abstract: Methods and apparatus are provided for improved iterative error-erasure decoding. A signal is decoded by obtaining a plurality of symbols associated with the signal and one or more corresponding reliability values; generating at least one erasure list comprised of L symbols and at least one shortened erasure list comprised of L? symbols, where L? is less than L; and constructing an erasure set by taking erasures from at least one of the erasure list and the shortened erasure list. A signal is also processed by generating one or more reliability values using a soft-output detector; generating an erasure list of symbols by comparing the reliability values to at least one reliability threshold value (or by sorting); and performing error erasure decoding using the erasure list. The size of the erasure list can optionally be adjusted using feedback information.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: August 21, 2012
    Assignee: Agere Systems Inc.
    Inventor: Erich F. Haratsch
  • Patent number: 8241986
    Abstract: The present invention, in one aspect, provides an integrated circuit that comprises a first region of transistors having gate structures with a low dopant concentration, and a second region of transistors having gate structures with a dopant concentration substantially higher than the gate structures of the first region, and wherein the transistors in the first region comprise a substantial portion of the integrated circuit. The transistors may include a resistor region located between an upper portion of the gate and the gate dielectric.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: August 14, 2012
    Assignee: Agere Systems Inc.
    Inventors: Taeho Kook, Tanya Nigam, Bonnie E. Weir
  • Patent number: 8242603
    Abstract: An integrated circuit (IC) structure includes a semiconductor substrate having a plurality of memory bits including IC identification information and a plurality of alternating metal and via layers thereabove. The IC structure includes a bond pad layer formed over a top one of the metal layers. The bond pad layer includes a plurality of pins connected to respective ones of the plurality of memory bits through the metal and via layers, at least one first pad connected to a higher voltage power supply rail and at least one second pad is connected to a lower voltage power supply rail. The bond pad layer has a plurality of circuit segments therein that each connects a respective one of the plurality of pins to either the at least one first pad or the at least one second pad for programming the IC identification information into the memory bit corresponding to that pin.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: August 14, 2012
    Assignee: Agere Systems Inc.
    Inventors: Joseph J. Check, Edward B. Harris, Lyle K. Mantz, II, Richard R. Kiser, Patricia J. Leith
  • Patent number: 8242378
    Abstract: A lead-free solder joint is formed between a tin-silver-copper solder alloy (SAC), SACX, or other commonly used Pb-free solder alloys, and a metallization layer of a substrate. Interaction of the SAC with the metallization layer forms an intermetallic compound (IMC) that binds the solder mass to the metallization layer. The IMC region is substantially free of any phosphorous-containing layers or regions.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: August 14, 2012
    Assignee: Agere Systems Inc.
    Inventors: Ahmed Amin, Frank Baiocchi, John Delucca, John Osenbach, Brian T. Vaccaro