Abstract: In a preferred embodiment, the invention is a mobile communication device having a digital signal processor (DSP), a speaker output node, a local audio source, and an analog front-end (AFE), wherein: (1) the DSP receives a first audio signal corresponding to sound captured by a microphone near a user of the device, (2) if the device is operating in a call mode, the DSP derives a background noise signal from the first audio signal, for subtraction from the first audio signal before transmission to the AFE, and (3) if the device is operating in a non-call mode, then the DSP (i) generates a speaker output signal which substantially corresponds to the first audio signal subtracted from a local audio signal provided by the local audio source and (ii) provides the speaker output signal to a speaker via the speaker output node.

Abstract: In one embodiment, the present invention is a low-density parity-check (LDPC) decoder that has a plurality of variable node units (VNUs) that generate variable node messages and a plurality of check node units (CNUs) that generate check node messages. The variable node messages and check node messages are distributed between the VNUs and CNUs using a number r of combinations of permutators, wherein each permutator combination includes (i) a cyclic shifter and (ii) a fixed, non-cyclic permutator. The cyclic shifters are capable of supporting a number p of different cyclic LDPC sub-matrices; however, when combined with different fixed permutators, the permutator combinations are capable of supporting up to r×p different LDPC sub-matrices. In other embodiments, the LDPC decoder may have fewer than r fixed permutators such that the LDPC decoder is capable of supporting between p and r×p different LDPC sub-matrices.

Abstract: Techniques for enhancing the performance of an IC are provided. A method of enhancing IC performance includes the steps of: associating at least one performance result of at least one performance monitor, formed on the IC, with deterministic combinations of IC performance and a processing parameter, a supply voltage, and/or a temperature of the IC; determining an IC processing characterization of the IC as a function of the performance result for at least one prescribed supply voltage and temperature of the IC, the IC processing characterization being indicative of a type of processing received by the IC during fabrication of the IC; and controlling a voltage supplied to at least a portion of the IC, the voltage being controlled as a function of the IC processing characterization and/or the temperature of the IC so as to satisfy at least one prescribed performance parameter of the IC.

Abstract: Various embodiments of the present invention provide systems and circuits that provide for LDPC decoding and/or error correcting. For example, various embodiments of the present invention provide LDPC decoder circuits that include a soft-input memory, a memory unit, and an arithmetic unit. The arithmetic unit includes a hardware circuit that is selectably operable to perform a row update and a column update. In such cases, a substantial portion of the circuitry of the hardware circuit used to perform the row update is re-used to perform the column update.

Abstract: An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.

Abstract: A memory device comprises a memory array and error correction circuitry coupled to the memory array. The memory device is configured to perform at least a partial word write operation and a read operation, with the partial word write operation comprising a read phase and a write phase. The write phase of the partial word write operation occurs in the same clock cycle of the memory device as the read operation by, for example, time multiplexing bitlines of the memory array within the clock cycle between the write phase of the partial word write operation and the read operation. Thus, the partial word write operation appears to a higher-level system incorporating or otherwise utilizing the memory device as if that operation requires only a single clock cycle of the memory device.

Abstract: Various embodiments of the present invention provide systems and methods for data regeneration. For example, a method for data regeneration is disclosed that includes receiving a data input derived from a medium, determining a media defect corresponding to the data input, and determining an attenuation factor associated with the defective medium. Based at least in part on the determination that the medium is defective, amplifying the data input by a derivative of the attenuation factor to regenerate the data.

Abstract: A wireless receiver detects signals received at two or more antennas, with each antenna coupled to an input receive chain. A switch is employed to couple selected input receive chains to one or more corresponding output receive chains during listening, coarse-detection, and fine-adjustment modes. At least one channel selection filter (CSF) is employed in each output receive chain, and the receiver employs sub-ranging. During idle mode, one antenna's input receive chain is connected to two or more CSFs to detect the packet. When the packet is detected, during a coarse-adjustment mode, the CSFs are reconfigured to couple each antenna's input receive chain to a corresponding output receive chain using low-gain signals. During fine-adjustment mode, the various gains are adjusted to be either high- or low-gain to maintain signals within the dynamic range of the corresponding CSFs.

Abstract: The present invention enhances the dynamic frequency selection 9DFS) algorithms used in Wireless LANs by adding a channel swapping mechanism. The aim of the traditional DFS algorithm is to dynamically select channels in a wireless LAN in such a way that the best performance is achieved. However, not always the optimal channel selection is achieved. This invention describes an addition to the DFS algorithm in such a way that two APs can decide to swap channels instead of one AP switching to another channel. To avoid the problem of sub-optimal channel selection, a requesting AP sends Swap Requests to other APs in order to sense the willingness of other APs to swap channels with the requesting AP.

Abstract: In one embodiment, a receiver has a reference generator and a main equalizer. The reference generator equalizes a received signal using one or more pilot reference signals. Then, the reference generator decodes one or more predetermined data channels of the equalized signal, makes hard decisions on the data of each decoded channel, and regenerates the original coding sequence of each decoded channel. The main equalizer uses each re-encoded channel as an additional reference signal along with one or more pilot signals to equalize a time-delayed version of the received signal. In alternative embodiments, the receiver might also have a step-size generator which selects optimum step sizes from a look-up table based on the number of re-encoded channels and the power of those channels. The step size is then used by the main equalizer along with the re-encoded channels to equalize the time-delayed received signal.

Abstract: A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors.

Abstract: An IC inductor structure is provided which includes a first inductor element formed on a semiconductor substrate and at least a second inductor element formed on the semiconductor substrate proximate the first inductor element. The first inductor element has a first effective magnetic field direction associated therewith, and the second inductor element has a second effective magnetic field direction associated therewith. The first and second inductor elements are oriented relative to one another so as to create a non-zero angle between the first and second effective magnetic field directions.

Abstract: In one embodiment, a virtual gateway mediates between a dual-mode subscriber device and an IP-based PBX. In particular, the virtual gateway includes a WLAN interface for communicating with the dual-mode subscriber device and a network interface (wired or wireless) for communicating with the IP-based PBX over the Internet. As such, the virtual gateway may relay voice and call control instructions between the dual-mode subscriber device and the IP-based PBX, and may provide the same call control functions to the dual-mode subscriber device provided by the call control processor in existing dual-mode phones. The embodiment further provides a dual-mode subscriber device suitable for operation with the virtual gateway. Because the dual-mode subscriber device does not require a call control processor, the battery life and cost of the device are significantly improved.

Abstract: Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply circuit that produces a regulated-output voltage based on an output-control signal generated by a resistive voltage divider. The circuit includes a PVT detector configured to generate an interface control signal and an interface circuit (i) connected to PVT detector and to the resistive voltage divider and (ii) configured to adjust its resistance in response to the interface control signal. Adjusting the resistance of the interface circuit causes the voltage of the output-control signal to be adjusted, thus causing the power supply circuit to adjust the regulated output voltage.

Abstract: In accordance with exemplary embodiments, a multi-level flash memory employs error correction of systematic errors when reading multi-level flash memory. Error correction includes i) detection of each systematic error, ii) feedback of the systematic error to circuitry within the memory, and iii) subsequent adjustment within that circuitry to cause a correction of systematic error in the output signal of the multi-level flash memory.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value.

Abstract: In one embodiment, the present invention generates a single rotation angle that may be used to maximize diversity of a quasi-orthogonal space-time block code that encodes groups of four data symbols. Two rotation angles corresponding the first two data symbols in a group are set to zero, and two rotation angles corresponding to the second two data symbols in a group are set to a single initial value. A codeword distance matrix is determined for each possible combination of codewords and erroneously decoded codewords that may be generated using the initial rotation angle, and the minimum of the determinants of these matrices is selected. This process is repeated to generate a plurality of minimum determinants, and, for each iteration, a different single rotation angle corresponding to the second two data symbols is used. Then, a single rotation angle is selected that corresponds to the maximum of the minimum determinants.

Abstract: Methods and apparatus are provided for storing survivor paths in a Viterbi detector. The invention maintains at least one register and at least one pointer for each state. Each register stores a bit sequence associated with a Viterbi state and each pointer points to one of the registers. One or more predefined rules based on a trellis structure are employed to exchange one or more of the pointers. A survivor path memory is also disclosed for a Viterbi detector. The survivor path memory comprises a plurality of columns, each associated with a different time step, and an input processor. Each column comprises a flip flop for storing one bit or portion of a bit sequence associated with a Viterbi state; and a multiplexer for each state controlled by a case signal indicating a time step, the multiplexer selecting a state from a previous time step, wherein an output of the multiplexer of a given state is connected to at least one data input of a flip flop of the given state.

Abstract: Proximity regulation systems for use with a portable cell phone and portable cell phones are disclosed. In one embodiment, a portable cell phone includes a proximity regulation system having a location sensing subsystem configured to determine a location of a portable cell phone proximate a user by determining a mode of operation of the portable cell phone. A power governing subsystem is coupled to the location sensing subsystem and configured to determine a proximity transmit power level of the portable cell phone based on the location.

Abstract: Various embodiments of the present invention provide circuits and methods for improved FET matching. As one example, such methods may include providing two or more transistors. Each of the transistors includes a channel that varies in cross-sectional width from the source to the drain, and the transistors are matched one to another.