Abstract: A fluid routing device includes a fluid inlet, first vertical channels, a horizontal channel, a second vertical channel, and a fluid outlet. The first vertical channels are open to the fluid inlet. The horizontal channel is open to each of the first vertical channels. The first vertical channels are oriented to provide fluid coolant from the fluid inlet vertically down to the horizontal channel. The horizontal channel is open on one side such that fluid coolant in the horizontal channel directly contacts an apparatus attached to a bottom of the fluid routing device. The second vertical channel is open to the horizontal channel. The second vertical channel is oriented to provide fluid coolant vertically up away from the horizontal channel. The fluid outlet is open to the second vertical channel such that fluid coolant from the second vertical channel exits the fluid routing device through the fluid outlet.

Abstract: The present embodiments relate to performing reduced-precision floating-point arithmetic operations using specialized processing blocks with higher-precision floating-point arithmetic circuitry. A specialized processing block may receive four floating-point numbers that represent two single-precision floating-point numbers, each separated into an LSB portion and an MSB portion, or four half-precision floating-point numbers. A first partial product generator may generate a first partial product of first and second input signals, while a second partial product generator may generate a second partial product of third and fourth input signals.

Abstract: Devices and methods of providing drivers for software and hardware systems to avoid additional polling or interrupt mechanisms are provided. An electronic device includes a processor supporting a device driver to perform a data packet receiving operation or data packet transmission operation. The device driver causes the processor to receive one or more data packets to a port of the processor according to a time-synchronization protocol. The device driver polls the DMA feature for a completion status of the storing. The device driver causes the processor to determine a timestamp of the one or more data packets and to complete the data packet receiving operation without the device driver causing the processor to perform a polling operation or an interrupt operation to retrieve the timestamp of the one or more data packets.

Abstract: Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit. The extraction/loading mechanism may also be implemented using multiplexers and associated control circuitry, scan chain circuitry, a memory-mapped interface, a tool-instantiated or user-instantiated finite state machine, or external memory interface logic. Accessing critical register states in this way can help improve efficiency with live migration events, debugging, retiming, and other integrated circuit operations.

Abstract: A method for implementing a convolutional neural network (CNN) accelerator on a target includes identifying characteristics and parameters for the CNN accelerator. Resources on the target are identified. A design for the CNN accelerator is generated in response to the characteristics and parameters of the CNN accelerator and the resources on the target.

Abstract: Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may be programmed with functions such as data/address manipulation functions, configuration/testing functions, computational functions, or the like.

Abstract: Circuits, methods, and apparatus are directed to an integrated circuit having a disabling element that can disable a reading of data from the circuit. Once the disabling element is set to not allow a reading of the data, the disabling element cannot be changed to allow a reading of the data. The data may be configuration data or internal data stored within the integrated circuit. Examples of the disabling element include a memory element, a break in a circuit line, and an input pad configuration.

Abstract: A method includes using a network interface controller to monitor a transmit ring, wherein the transmit ring comprises a circular ring data structure that stores descriptors, wherein a descriptor describes data and comprises a guest bus address that provides a virtual memory location of the data. The method also includes using the network interface controller to determine that a descriptor has been written to the transmit ring. The method further includes using the network interface controller to attempt to retrieve a translation for the guest bus address. The method includes using the network interface controller to read the descriptor from the transmit ring.

Abstract: A method for designing a system on a target device includes performing register retiming on an original design to generate a retimed design of the system. Compare points are identified in the original design and the retimed design. Equality constraints are defined for all compare points. Starting from the initial states of the original and retimed circuits, bounded sequential logic simulation is performed for a maximum number of time frames determined as the maximum absolute value of retiming variables computed during structural verification. Whether changed flip-flops in the retimed design have initial states that are correct are determined by comparing signal values at the compare points from the bounded sequential logic simulation.

Abstract: The present embodiments relate to regulating the supply voltage of an integrated circuit. The integrated circuit may implement a circuit design. The circuit design implementation may meet timing constraints with timing margins when operated with the integrated circuit at a nominal supply voltage level. The integrated circuit may further include a voltage identification controller. The voltage identification controller may determine a reduced voltage level based at least on the timing margins such that operating the circuit design implementation with the integrated circuit meets timing constraints. The voltage identification controller may direct a voltage regulator, which may be included in the integrated circuit or located outside the integrated circuit, to reduce the supply voltage level from the nominal supply voltage level to the reduced voltage level, thereby reducing the power consumption of the integrated circuit.

Abstract: A programmable integrated circuit with lookup table circuitry is provided. The lookup table (LUT) circuitry may be formed using multiplexers. A multiplexer in the lookup table circuitry may be implemented using only tristate inverting circuits. Each tristate inverting circuit may include a first set of n-channel and p-channel transistors that receive a static control bit from a memory element and a second set of n-channel and p-channel transistors that receive true and complementary versions of a user signal. The first and second sets of transistors may be coupled in series between a positive power supply terminal and a ground power supply terminal. A LUT multiplexer implemented in this way need not include separate transmission gates at the output of each tristate inverting circuit and may exhibit minimal subthreshold leakage.

Abstract: A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.

Abstract: A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.

Abstract: The present embodiments relate to integrated circuits with floating-point arithmetic circuitry that handles normalized and denormalized floating-point numbers. The floating-point arithmetic circuitry may include a normalization circuit and a rounding circuit, and the floating-point arithmetic circuitry may generate a first result in form of a normalized, unrounded floating-point number and a second result in form of a normalized, rounded floating-point number. If desired, the floating-point arithmetic circuitry may be implemented in specialized processing blocks.

Abstract: Systems and methods for configuring a SPA are disclosed. The SPA comprises a plurality of input ports, a plurality of data memory units, signal processing circuitry, and an enable block including at least two counters. Each counter determines an amount of unprocessed data that is stored in a respective one of the plurality of data memory units, and the enable block is configured to disable the signal processing circuitry until a predetermined amount of data is received over the input ports.

Abstract: A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. Whether the retimed design is structurally correct is verified by performing register retiming on the retimed design.

Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Register retiming is performed where pipeline registers are added at boundaries of the area.

Abstract: An integrated circuit includes a control circuit and a one-time programmable circuit. The control circuit determines if the one-time programmable circuit is programmed in response to an attempt to access a mode of the integrated circuit after the integrated circuit powers up. The control circuit generates a signal to indicate to a user of the integrated circuit that the mode of the integrated circuit has been previously accessed if the control circuit determines that the one-time programmable circuit has been programmed to indicate a previous access to the mode of the integrated circuit.

Abstract: Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.

Abstract: Integrated circuits with specialized processing blocks are provided. A specialized processing block may include one real addition stage and one real multiplier stage. The multiplier stage may simultaneously feed its output to the addition stage and directly to an adjacent specialized processing block. The addition stage may also produce sum and difference outputs in parallel. A group of four such specialized processing blocks may be connected in a chain to implement a radix-2 fast Fourier transform (FFT) butterfly. Multiple radix-2 butterflies may be stacked to form yet higher order radix butterflies. If desired, the specialized processing block may also be used to implement a complex multiply operation. Three or four specialized processing blocks may be chained together and along with one or more adders outside the specialized processing blocks, real and imaginary portions of a complex product can be generated.