Abstract: A proportional to absolute temperature, PTAT, circuit is provided. By judiciously combining circuit elements it is possible to generate a voltage at an output node of the circuit that is temperature dependent. Such a PTAT circuit can be used as a temperature sensor or can be combined with other temperature dependent circuits to provide a voltage reference.

Abstract: A power converter can include an electrical isolation circuit between input and output nodes. An input signal monitor node can be provided, such as on a converter output side of the isolation circuit. In an example, a peak detection circuit can be coupled to the input signal monitor node. The output node of the power converter can be configured to supply an output power signal that is a function of an input signal at the input node. The power converter can include multiple, independently-switchable switches at one or more of the input and output sides of the isolation circuit. In an example, the power converter with the input signal monitor node can be configured as a bias supply to provide power, at the output node, to a controller circuit for a main stage power converter circuit.

Abstract: A method for detecting a preamble in a received radio signal comprises demodulating a received radio signal based on a carrier derived from a local timing source to provide a digital signal comprising a sequence of bits oscillating at approximately a modulated data rate. A bit width of each successive bit of the digital signal is determined. If a pair of consecutive bit widths have a combined width within a threshold value, the bit pair is indicated as potentially belonging to a preamble. If a threshold number of potential preamble bit pairs in a sequence of bit pairs within a given window is detected, the sequence of bit pairs is indicated as potentially comprising a preamble. A measure of bit widths of at least some bits within a sequence of preamble bit pairs can be provided and a frequency of the local timing source can be adjusted according to said measure.

Abstract: A low-cost system comprising a pattern arranged to encode information and a decoder for decoding the information encoded in the pattern is described. In particular, the mechanism employs a capacitive sensing technique. Electrodes are arranged (or stimulated, during operation) to each generate an electric field, and sense disturbances on the electric field caused by the pattern when the pattern is positioned over the electrodes. The spatial arrangement of the pattern allows information to be encoded on a strip or surface and decoded by capacitive sensors arranged to detect disturbances caused by possible patterns. The resulting solution is cheaper and less complex than optical solutions, e.g., barcodes and optical barcode readers. The mechanism may be used in a glucose meter for encoding and decoding an identifier for distinguishing batches of glucose meter test strips.

Abstract: An exemplary object detection method includes generating feature block components representing an image frame, and analyzing the image frame using the feature block components. For each feature block row of the image frame, feature block components associated with the feature block row are evaluated to determine a partial vector dot product for detector windows that overlap a portion of the image frame including the feature block row, such that each detector window has an associated group of partial vector dot products. The method can include determining a vector dot product associated with each detector window based on the associated group of partial vector dot products, and classifying an image frame portion corresponding with each detector window as an object or non-object based on the vector dot product. Each feature block component can be moved from external memory to internal memory once implementing the exemplary object detection method.

Abstract: A modulation scheme for long range transceiver utilizing a processing scheme in combination with a Hadamard transform is disclosed. The processing scheme can correspond to an industry standard or to other processing schemes. An input signal is parallelized through serial to parallel conversion. The processed parallel signals are orthogonalized using a Hadamard transform to allow multiple channel signals with increased throughput. Accordingly, the long range modulation scheme of this invention can achieve high efficiency and increased throughput while meeting performance goals of long range signal transmission.

Abstract: A stress shield for a plastic integrated circuit package is disclosed. A shield plate is attached by an adhesive to a top surface of an integrated circuit die such that the shield plate covers less than all of the top surface and leaves bond pads exposed. A molding material is applied over the shield plate and the integrated circuit die. The shield plate shields the integrated circuit die from stresses imparted by the molding material.

Abstract: In one example implementation, the present disclosure provides a loop filter for use in a continuous-time sigma-delta analog-to-digital converter. Specifically, a capacitive feedback digital-to-analog converter path is provided at the input of a first opamp in a series of opamp integrators. The capacitive feedback digital-to-analog converter at the input of the first opamp reduces the signal content at the output of the first opamp, and thereby reduces the output swing of the first opamp. A reduction in output swing provides a more efficient loop filter.

Abstract: An analog-to-digital converter (ADC) can include a continuous-time delta sigma modulator and calibration logic. The calibration logic can calibrate direct feedback and flash clock delay coefficients of the continuous-time delta-sigma modulator without interrupting the normal operations of the ADC (e.g., in situ). Thus, the calibration logic can rectify performance and stability degradation by calibrating suboptimal coefficients.

Abstract: A switching regulator or other apparatus or techniques can include load current monitoring to provide a digital representation of an estimated load current. Load current monitoring can be performed by a circuit including a counter circuit, a comparator circuit, and a digitally-controlled source coupled to the counter circuit and configured to adjust a bias condition of a sensing device in response to a count provided by the counter circuit in order to establish a proportional relationship between a current conducted by the sensing device and a corresponding current conducted by a power switching device. The counter circuit is configured to increment and decrement the count in response to information provided by the comparator output and the count is generally indicative of the estimated load current, such as an average load current.

Abstract: A transmission system may include a transformer, an adder, an encoder, and a transmitter. The transformer may segment and transform a data packet into segments. The adder may add a check code to each of the segments. The encoder may encode error correction to each of the segments with the added check code. A receiving system may include a receiver, a decoder, a checker, and a selector decoder. The decoder may decode error correction in each of the encoded segments. The checker may check the check code of the error corrected segments. The selector decoder may select at least one of the valid segments based upon the check code and transform the selected segments into a data packet.

Abstract: The present disclosure describes an improved multi-stage noise shaping (MASH) analog-to-digital converter (ADC) for converting an analog input signal to a digital output signal. In particular, a full delta-sigma (??) modulator is provided at the front-end of the MASH ADC, and another full ?? modulator is provided at the back-end of the MASH ADC. The front-end ?? modulator digitizes an analog input signal, and the back-end ?? modulator digitizes an error between the output of the front-end ?? modulator and the (original) analog input signal. In this configuration where the back-end modulator digitizes the error of the (full) front-end modulator, some design constraints of the front-end are relaxed. These design constraints include thermal noise, digital noise cancellation filter complexity (the quantization noise of the front-end is already shaped by the noise transfer function of the front-end), and/or non-linearity.

Abstract: A delta-sigma modulator is configured to sense and convert an electromagnetic field into a digital signal. An exemplary delta-sigma modulator includes a sensor component, such as an LC resonator, that is configured to sense the electromagnetic field and generate an input analog signal, where the delta-sigma modulator is configured to convert the input analog signal to the digital signal. Delta-sigma modulator can include an analog-to-digital converter coupled to the sensor component that receives and converts the input analog signal to the digital signal. Delta-sigma modulator can further include a digital-to-analog converter (DAC) coupled to the resonator and the ADC, the DAC configured to receive the digital signal from the ADC and generate a feedback analog signal.

Abstract: A circuit may include a plurality of primary digital-to-analog (DAC) elements for converting a digital input signal into an analog output signal. A control circuit may control each primary DAC element to switch between a first state and a second state based on the digital input signal to provide the analog output signal at an output representing the digital input signal. A plurality of corrective DAC elements may be coupled in parallel to the plurality of primary DAC elements between the control circuit and the output. The plurality of corrective DAC elements may be controlled to mitigate for intersymbol interference (ISI) due to parasitic capacitance in the primary DAC elements. The plurality of corrective DAC elements may not contribute a direct current to the analog output signal.

Abstract: A method of forming a junction field effect transistor, the transistor comprising: a back gate; a channel; a top gate; a drain and a source in current flow with the channel; wherein the method comprises selecting a first channel dimension between the top gate and the back gate such that a significant current flow path in the channel occurs in a region of relatively low electric field strength.

Abstract: A digital-to-analog converter (DAC) comprising a first section having a first plurality of current flow paths forming binary weighted values in the DAC; and a second section connected to the first section and having a second plurality of current flow paths, wherein each of the first and second plurality of current flow paths are switchable between first and second nodes, and wherein weights of one or more of the second plurality of current flow paths are notionally equal to weights of one or more of the first plurality of current flow paths so as to provide redundancy in the first section.

Abstract: A multi-level amplifier including a converter circuit being supplied with a supply voltage and operable to generate at least two output voltages, a voltage comparator circuit adapted to compare each of the output voltages with the supply voltage to generate a driving signal, and an amplifier circuit being supplied with an analog input signal, the amplifier circuit including an analog-to-digital converter coupled to a power stage driver and power stage, wherein the power stage driver receives the driving signal from the voltage comparator.

Abstract: An analog to digital converter comprising at least one sampling capacitor connected to a sample node, and a pre-charge circuit arranged to cause the voltage on the sample node to substantially match the input voltage prior to the analog to digital converter entering an acquire mode in which the sample node is connected to the input node by a sample switch.

Abstract: Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.

Abstract: A monitoring circuit for monitoring the performance of a phase locked loop having a divider therein, the divider comprising at least a first counter, the monitoring circuit comprising at least one memory element for capturing a value of the first counter after a predetermined time from a system event in the operation of the phase locked loop, a variability calculator for comparing a value of the counter with a preceding value of the counter to calculate a variation, and a circuit responsive to the estimate of variation for outputting a status signal.