Abstract: Apparatus and methods for generating a drive signal of a switching signal are disclosed. A first circuit receives an oscillating reference signal, a first compensation signal, a second compensation signal, and a third compensation signal. The first compensation signal is indicative of an error between an output voltage of a power converter and a reference voltage. The second compensation signal is indicative of the error relative to a threshold. The third compensation signal is indicative of an output current of the power converter. The first circuit generates a comparison signal having a waveform including pulses having durations based at least partly on a combination of the periodic reference signal, the first compensation signal, the second compensation signal, and the third compensation signal. A second circuit receives a clock signal and the comparison signal and generates a drive signal for activation and deactivation of a driver transistor.

Abstract: In one aspect, an electrical signal converter is disclosed. The exemplary electrical signal converter may include a plurality of ordered converter elements. Element selection logic may be provided to pseudorandomly select a pointer to a switch matrix, wherein the switch matrix maps converter elements according to a stepwise “delta-two-maximum pattern.” Advantageously, pseudorandom stepwise delta-two-maximum patterns may be applied both to a first order converter, and to a feedback converter for error correction.

Abstract: Embodiments of the present invention may provide a multi-string DAC with leakage current cancellation. A leakage cancellation circuit may be coupled to output node(s) of the—multi-string DAC. The leakage cancellation circuit may replicate leakage current present at the coupled output node(s) and generate a corresponding complementary signal, a leakage cancellation signal. The leakage cancellation signal may be injected into the coupled output node(s) to cancel (or reduce) the net impact of the leakage current.

Abstract: Embodiments of the present invention may provide a string DAC with charge boosting. The string DAC may include multiple strings, such as an MSB DAC and an LSB DAC, for converting a digital word into a corresponding analog voltage. The string DAC may also include a charge boost system to couple a charge into or out of the DAC during a code transition, such as a MSB code transition. The string DAC may operate in a break-before-make connection technique where all relevant connections are substantially open-circuited before new connections are made. Therefore, the charge boost may shorten the settling time of impedance elements in the string DAC between code transitions and may substantially reduce (or eliminate) glitches.

Abstract: In at least one example embodiment, a microprocessor circuit is provided that includes a microprocessor core coupled to a data memory via a data memory bus comprising a predetermined integer number of data wires (J); the single-ported data memory configured for storage of vector input elements of an N element vector in a predetermined vector element order and storage of matrix input elements of an M×N matrix comprising M columns of matrix input elements and N rows of matrix input elements; a vector matrix product accelerator comprising a datapath configured for multiplying the N element vector and the matrix to compute an M element result vector, the vector matrix product accelerator comprising: an input/output port interfacing the data memory bus to the vector matrix product accelerator; a plurality of vector input registers for storage respective input vector elements received through the input/output port.

Abstract: A predetermined nonlinearity may be introduced between a digital predistorter and a power amplifier of a RF transmitter. The nonlinearity may be applied to an output of a digital predistorter. The application of the nonlinearity to the predistorter output may expand a bandwidth of the predistorter output from a first lower bandwidth to a higher second bandwidth of the power amplifier that may be needed to support a predetermined data transfer rate at the RF transmitter. Introducing this nonlinearity between the predistorter and the power amplifier may reduce the sampling rate and power requirements of components included as part of a predistortion device. As a result less noise may be generated and less power may be consumed, resulting in smaller, more efficient, and more accurate predistortion and/or RF transmission systems.

Abstract: Apparatus and methods for current sensing in switching regulators are disclosed. In certain implementations, a current sensing circuit senses current of a power stage of a power converter. The power converter can include first and second transistors. The current sensing circuit comprises a transistor that is a scaled version of one of the transistors of the power converter. A circuit of the current sensing circuit matches a drain-to-source voltage of the transistor of the current sensing circuit to the corresponding transistor of the power converter. A current mirror generates a current that mirrors the current flowing through the transistor of the current sensing circuit. A first resistor converts the mirrored current to a current sensed signal.

Abstract: A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.

Abstract: An apparatus includes a processing unit that divides an overlay buffer into a plurality of macro blocks, draws a graphic primitive object including a plurality of pixels, identifies one of the plurality of macro blocks upon a determination that the plurality of pixels has crossed a boundary of the one of the plurality of macro blocks, and image processes the one of the plurality of macro blocks.

Abstract: An example transconductance circuit is provided in accordance with one embodiment. The transconductance circuit can comprise: an output node; at least one transistor; a variable resistance; and a differential amplifier; wherein the at least one transistor and the variable resistance are in series connection with the output node, an output of the differential amplifier is connected to a control node of the at least one transistor, a first input of the amplifier is responsive to an input signal, and a second input of the amplifier is responsive to a voltage across the variable resistance. Such a circuit may overcome noise problems in transconductance circuits which operate over a wide range of input signals with a fixed resistor in series with the at least one transistor.

Abstract: Dual-tub junction-isolated voltage clamp devices and methods of forming the same are provided herein. The voltage clamp device can provide junction-isolated protection to low voltage circuitry connected between first and second high voltage interface pins. In certain implementations, a voltage clamp device includes a PNPN protection structure disposed in a p-well, a PN diode protection structure disposed in an n-well positioned adjacent the p-well, a p-type tub surrounding the p-well and the n-well, and an n-type tub surrounding the p-type tub. The p-type tub and the n-type tub provide junction isolation, the p-type tub can be electrically floating, and the n-type tub can be electrically connected to the second pin. The first and second pins can operate at a voltage difference below the junction isolation breakdown, and the second pin can operate with higher voltage than the first pin.

Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.

Abstract: A method can reuse at least one pin in demultiplexing (demuxing) a voltage from a pin. The method can be used to set an accurate current limit threshold in a design for test (DFT) phase and, thus, to accurately set a trimming code of a current limiter. The method uses the property that a power MOSFET has almost a same conductive resistance at a large drain current. Thus, the current limit threshold can be set according to an accurate drain-to-source voltage Vds at a small current sink that is less than a maximum current that ATE is able to provide. An accurate voltage Vds can be measured through Kelvin sensing drain and source pins of the power MOSFET, which are connected to a current sense circuit.

Abstract: A flash ADC circuit may include a reference ladder providing reference signals and a plurality of comparators, each providing an output based on a comparison of a pair of input signals to a pair of reference signals. At least one pair of the comparators may receive the same pair of reference signals with a different orientation of the reference signals at each of the comparators. The flash ADC may include a switch network for swapping the pair of reference signals between the pair of comparators.

Abstract: A transformer based isolated bi-directional DC-DC power converter may have signals for controlling power transfer in first and second directions are derived from the same side of the transformer. The converter may include a transformer, a first switching circuit, a second switching circuit, and a controller. In a first mode, the controller controls the first and second switching circuits, and power is transferred from a first side to a second side. In a second mode, the controller controls the first and second switching circuits, and power is transferred from the second side to the first side.

Abstract: A circuit and a system that uses the circuit for connecting a plurality of input channels to a receiving device. The circuit includes a plurality of DMOS switches, each of which connects a respective one of the input channels to the receiving device in response to a respective control signal. The control signals are referenced to a ground signal. Each input channel includes a common mode voltage that is non-referenced to the ground signal. The circuit also includes a switch driver that generates the control signals such that the input channels are activated one at a time.

Abstract: A multi-string DAC is described and comprises at least two DAC stages. Each DAC stage comprises a string of impedance elements and a switching network. In one configuration, the DAC comprises a first and second switching network, the second switching network providing multiple switched paths which compensate for impedance effects of the second string and provides multiple state changes at the output node of the DAC.

Abstract: An apparatus for transferring charge has a first charge pump path with a plurality of stages having first capacitors, and a second charge pump path, also with a plurality of stage having second capacitors, in parallel with the first charge pump path. The first and second charge pump paths are coupled to share a common output node. The apparatus also has a timing circuit coupled with the first and second charge pump paths. Among other things, the timing circuit is configured to cause at least one of the first capacitors to periodically charge at least one of the second capacitors.

Abstract: A converter system, including a first converter that digitizes the a first portion of an input signal, the first converter including a comparator, a timer having a circuit structure that emulates a circuit structure of a comparator in the first converter, the timer receiving an input signal indicating commencement of operations in the comparator, a second converter that digitizes a second portion of the input signal remaining from the first portion in response to an output from the timer, and a combiner having inputs to generate a digital code from the digitized first and second portions.

Abstract: A locking/unlocking mechanism for a contactless gesture detection system of a device is described herein. The locking/unlocking mechanism can facilitate automatic locking, manual locking, and/or manual unlocking of the contactless gesture detection system. The contactless gesture detection system can implement the locking/unlocking mechanisms described herein to control a contactless gesture-based user interface state of the device. In various implementations, the controlling can include detecting gestures associated with a user in a contactless space associated with the device; detecting a defined gesture sequence over a defined time period from the detected gestures; and transitioning the device to a contactless gesture-based user interface locked state or a contactless gesture-based user interface unlocked state based on the defined gesture sequence.