Abstract: In one aspect, there is disclosed a digital signal processor and method performed by the same for performing object detection, including facial detection, in a reduced number of clock cycles. The method comprises using Sobel edge detection to identify regions with many edges, and classifying those regions as foreground candidates. Foreground candidates are further checked for vertical or horizontal symmetry, and symmetrical windows are classified as face candidates. Viola-Jones type facial detection is then performed only on those windows identified as face candidates.

Abstract: A digital-to-analog (DAC) element may include a plurality of switches arranged to form two circuit branches between a current source and a first and a second outputs. The first circuit branch may include two switches defining parallel current paths between the current source and the first output terminal. The second circuit branch may include two switches defining parallel current paths between the current source and the second output terminal. A control circuit, responsive to an input signal that selects one of the circuit branches, may provide control signals to close one of switches in the selected circuit branch in a first portion of a clock cycle and to close the other of the switches in the selected circuit branch in a second portion of the clock cycle.

Abstract: Embodiments of the present invention may include power amplifier architectures and systems for use in wireless communication systems. The systems may include a first circuit path for receiving an input signal and decomposing the signal into two vector signals using an out-phasing generator, modifying the vectors based on predetermined value limit, amplifying the vectors using power amplifiers, and combining the vectors to provide an amplified output. The system may include a second circuit path for generating an estimate of an envelope of the input signal and using the envelope to modulate the voltage supplies of the power amplifiers when amplifying the vector signals. The system may also include a feedback path for sending information regarding the envelope of the input signal into the out-phasing generator, which may modify the vector signals in response thereto.

Abstract: A method for tracing edges of an image using hysteresis thresholding includes: (i) receiving an edge map of the image, (ii) scanning one row of the input edge map, (iii) assigning a label to each edge pixel in the row based at least in part on the presence or absence of a neighboring edge pixel, (iv) grouping contiguous labels, and (v) identifying groups of edge pixels.

Abstract: A microprocessor circuit may include a software programmable microprocessor core and a data memory accessible via a data memory bus. The data memory may include sets of configuration data structured according to respective predetermined data structure specifications for configurable math hardware accelerators, and sets of input data for configurable math hardware accelerators, each configured to apply a predetermined signal processing function to the set of input data according to received configuration data. A configuration controller is coupled to the data memory via the data memory bus and to the configurable math hardware accelerators. The configuration controller may fetch the configuration data for each math hardware accelerator from the data memory and translate the configuration data.

Abstract: A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.

Abstract: A MEMS switch device including: a substrate layer; an insulating layer formed over the substrate layer; and a MEMS switch module having a plurality of contacts formed on the surface of the insulating layer, wherein the insulating layer includes a number of conductive pathways formed within the insulating layer, the conductive pathways being configured to interconnect selected contacts of the MEMS switch module.

Abstract: A driver may provide a transition of a switch between an on state and an off state in two stages. In the first stage, the voltage slew rate of the voltage at an output terminal of the switch may be controlled. In the second stage, the current gradient of the switch may be controlled. The transition between the first stage and the second stage may be made based on the value of the voltage at the output terminal of the switch.

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract: An electrical circuit includes a local oscillator configured to generate a first reference signal and a second reference signal having a predetermined phase shift with the first reference signal, an I-channel mixer configured to inject the first reference signal to an incoming signal and generate a first output, a compensation mixer configured to multiply the first output with a constant factor to generate a second output, a first low pass filter configured to approximately attenuate frequencies in the second output to generate a third output, and a first correcting filter configured to filter the third output to generate a fourth output. The first correcting filter is configured to reduce a channel impulse response mismatch between the first low pass filter and a second low pass filter, which is configured to attenuate frequencies in a Q-channel of the incoming signal. In specific embodiments, the phase shift includes 45°.

Abstract: In one example, there is disclosed a hybrid analog-digital point-of-load controller (ADPOL) for use in a power supply. The ADPOL is configured to respond to transient current loads. In the presence of moderate current transients, power is clocked by a digital power core, which may be programmatically configured to adjust pulse width in response to the transient. In the presence of larger current transients, control may be passed to an analog transient compensator, which includes high-speed circuitry selecting between a very high-duty-cycle clock and a very low-duty-cycle clock, which will drive the transient back to the digital control domain.

Abstract: A circuit may include a detector, a modulator, a switch, and a stabilizer. The detector may detect current supplied to an output of the circuit to generate an overcurrent signal. The modulator may modulate a pulse signal based upon the output of the circuit. The switch may control a power stage to generate the output of the circuit based upon the overcurrent signal and the pulse signal. The stabilizer may send an offset signal to the modulator. The stabilizer may generate the offset signal with a magnitude adjusted based upon the overcurrent signal, and the modulator may adjust the pulse signal based upon the offset signal.

Abstract: A power stage to generate an output voltage at one of a high reference voltage, an intermediate reference voltage and a low reference voltage, including a first switch stage connecting the output terminal to the high reference voltage, comprising a pair of transistors connected in series along their source-to-drain paths, a first transistor coupled to the output terminal and having its gate biased at the intermediate voltage, a second transistor having a gate that receives a first stage control signal that varies between the high reference voltage and the intermediate reference voltage, a second switch stage connecting the output terminal to the intermediate reference voltage, having a gate that receives a second stage control signal that varies among the high reference voltage, intermediate reference voltage and low reference voltage, a third switch stage connecting the output terminal to the low reference voltage, having a pair of transistors connected in series along their source-to-drain paths, a first tr

Abstract: A method includes determining a position and length of a non-zero run in a row of a pixel map. The method also includes determining a number of neighbors for the non-zero run in a preceding row, based at least in part on the position and the length. In addition, the method includes updating a correspondence map of the non-zero run and a correspondence map of a first neighbor of the non-zero run, based at least in part on a correspondence map of a second neighbor of the non-zero run, in response to a determination that the non-zero run has at least two neighbors in the preceding row.

Abstract: A digital input to a digital-to-analog converter (DAC) is divided into a most significant portion and a lesser significant portion. At least one tap voltage generator generates a plurality of voltages, preferably using a resistor string. A decoder decodes at least one sub-word that forms the lesser significant portion to generate a corresponding at least one control signal. A switching unit accesses voltages generated by the at least one tap voltage generator in response to the at least one control signal. A scaled current generator generates a respective weighted current from each accessed voltage. An output stage combines all the weighted currents with a voltage that is an analog representation of the most significant portion of the digital input to generate an analog approximation of the entire digital input.

Abstract: A method and system to inhibit the switching of a current mode switching converter having high and low side switching elements coupled to an output inductor, the other end of which is coupled to an output node, and operated with respective modulated switching signals to regulate an output voltage Vout produced at the node. A current IC that varies with the difference between a reference voltage and a voltage proportional to Vout is compared with and a current IDETECT—PEAK which varies with the current conducted by the high side switching element; the result of the comparison of IC and IDETECT—PEAK is used to control the regulation of Vout during normal operation. Current IC is also compared with a current IDETECT—VALLEY which varies with the current conducted by the low side switching element. When IDETECT—VALLEY>IC, a ‘skip mode’ is triggered during which the switching signals are inhibited.

Abstract: A system may include a detector, a controller, a shuffler, and a processor. The detector may detect a signal. The controller may control the shuffler based upon the signal. The shuffler may shuffle a plurality of channels at the input of a plurality of processing elements of the processor based upon the signal. The processor may process the signal according to the plurality of channels as configured by the shuffler.

Abstract: An integrated circuit includes a component calculator configured to compute at least one component value of a highly programmable analog-to-digital converter (ADC) from at least one application parameter, and a mapping module configured to map the component value to a corresponding register setting of the ADC based on at least one process parameter, wherein the integrated circuit produces digital control signals capable of programming the ADC. In a specific embodiment, the component calculator uses an algebraic function of a normalized representation of the application parameter to approximately evaluate at least one normalized ADC coefficient. The component value is further calculated by denormalizing the normalized ADC coefficient. In another specific embodiment, the component calculator uses an algebraic function of the application parameter to calculate the component value.

Abstract: Apparatus and methods for current sensing in switching regulators are provided. In certain implementations, a switching regulator includes a switch transistor, a replica transistor, a sense resistor, and a current sensing circuit. The drain and gate of the switch transistor can be electrically connected to the drain and gate of the replica transistor, respectively. The current sensing circuit can generate an output current that varies in response to a sense current from a source of the replica transistor. Additionally, the current sensing circuit can sink the sense current when the sense current flows from the drain to the source of the replica transistor and source the sense current when the sense current flows from the source to the drain of the replica transistor. The sense resistor can receive the output current such that the voltage across the sense resistor changes in relation to the current through the switch transistor.

Abstract: Various digital pre-distortion systems for use in transmitters are disclosed. The digital pre-distortion system comprises an observing path, which performs either undersampling or radio frequency sampling of the output of a power amplifier. Undersampling may be performed at a rate, which causes aliasing to occur in the undersampled frequency domain. Both undersampling and radio frequency sampling reduces the complexity of the digital pre-distortion system by removing any down mixing modules or anti-aliasing modules, while maintaining reasonable performance of the digital pre-distortion systems.