Abstract: An apparatus and method dynamically controls the graphics and/or video memory power dynamically during idle periods of the memory interface during active system modes. In one embodiment, a memory request detector generates memory request indication data, such as data representing whether memory requests have been received within a predetermined time, based on detection of graphics and/or video memory requests during an active mode of the display system operation. A dynamic activity based memory power controller analyzes the memory request indication data and controls the power consumption of the graphics and/or video memory based on whether memory requests are detected.

Abstract: A method and apparatus for utilizing a data cache in a system with both 2D and 3D graphics applications. In a specific embodiment of the present invention, a mode signal is received by the video system indicating whether a 2D or 3D application is to be used. Depending on the mode signal, either as a unified cache capable of being accessed by two separate data access streams, or two independent caches, each accessed by one data access stream.

Abstract: A method and apparatus for utilizing mip maps in a video graphics system begins by setting a dynamically configurable level of detail bias that is used to select between potential mip maps. The level of detail bias is set based on the screen resolution. The selection of the mip map, or mip maps, utilized for texturing operations with respect to a particular pixel is performed based on the configurable level of detail bias and the texel-per-pixel ratio between the potential mip maps and the particular pixel to be textured. The dynamic configuration of the level of detail bias allows texture detail to be maintained across multiple display resolutions.

Abstract: An instruction aligner and method evaluates a fixed length instruction cache line by breaking it into at least two components. These two components, in one embodiment, include half of the instruction cache line being designated as most significant bytes and the second half of the instruction cache line being designated as least significant bytes. A byte right rotator is responsible for feeding the next sixteen bytes of the instruction stream, while a byte right shifter shifts the unused bytes of the current sixteen bytes the aligner is working on. The byte rotator and byte shifter combine to provide aligned variable length instructions for decoding based on either a fetch PC value or current instruction length.

Abstract: A circuit for texture tag checking includes a first comparison gate which compares a first dimension field of a tag with a first dimension element for a group of texels associated with a sample point. A second comparison gate compares a second dimension field of the tag with a second dimension element for the group of texels. A logic gate, coupled to each of the first and second comparison gates, is associated with one texel of the group of texels. The logic gate outputs a predetermined signal if the first and second dimension fields of the tag are the same as the first and second dimension elements, respectively.

Abstract: A floating point register stack for a processor combines a plurality of two general purpose registers to form a register stack for x86 instructions and leaves the remaining general purpose registers for native instructions of the processor. By mapping x86 sources into the stack of two general purpose registers and operating x86 instructions on the x86 stack, the register stack for the processor is able to support both the processor's native instruction set and the x86 instruction set without increasing the size of the register stack.

Abstract: A phase locked loop (PLL) circuit adjusts a voltage controlled differential oscillator to generate an output frequency signal, which is a selected multiple of an input reference signal. The PLL circuit includes an oscillator control circuit for increasing and decreasing the PLL output frequency signal, a frequency detector for detecting a phase shift between the reference signal and the PLL output signal and produces an error signal, and a fast lock circuit for detecting when the output frequency signal passes the selected multiple of the reference signal. This circuit design provides improved jitter performance, tolerates process variation, and extends the PLL operating frequency range.

Abstract: A method and apparatus for arithmetic shifting includes processing that begins by receiving a decoded instruction in a cycle of a pipeline process. Also during this cycle of the pipeline process, shift information and a data operand are determined based on the decoded instruction. In a subsequent cycle of the pipeline process, a data output is generated from the data operand based on the shift information using a crossbar shifting function.

Abstract: A request for video or graphics data is made to a memory controller. When the memory controller determines a translation of the data must first be made, a request is made to a translator. The translator either translates the address or requests translation information from the memory controller. The memory controller accesses memory based upon the translator request. If the request is for translation data the results are tagged for the translator. If the translator request is for the translated address, the results are tagged for the original request.

Abstract: An integrated computing system includes at least one processor formed on a substrate, wherein the processor operates at a processor rate. The integrated computing system further includes a global bus that is coupled to the at least one processor and is formed on the substrate. The global bus supports transactions (e.g., data, operational instructions, and/or control signaling conveyances) at a rate that is equal to or greater than the processing rate. The integrated computing system further includes a device gateway and memory gateway that are operably coupled to the global bus and formed on the substrate. The device gateway provides an interface for at least one device (e.g., internal or external) to the global bus. The memory gateway provides an interface between the global bus and memory.

Abstract: A method and apparatus for arbitrating access to a computation engine includes processing that begins by determining, for a given clock cycle of the computation engine, whether at least one operation code is pending. When at least one operation code is pending, the processing continues by providing the operation code to the computation engine. When multiple operation codes are pending for the given clock cycle, the processing determines a priority operation code from the multiple pending operation codes based on an application specific prioritization scheme. The application specific prioritization scheme is dependent on the application and may include a two level prioritization scheme. At the first level the prioritization scheme prioritizes certain threads over other threads such that the throughput through the computation module is maximized.

Abstract: A graphics processing system that includes a graphic processing circuit and an enhanced memory circuit is presented. The graphics processing circuit performs the rendering of graphics primitives to produce pixel fragment data. The pixel fragment data is then grouped into fragment blocks that are compressed and sent across a bus of limited bandwidth in an efficient manner to the enhanced memory circuit. Within the enhanced memory circuit, the compressed fragment blocks are decompressed and restored to their original state. Comparison and blending operations are then performed on a block-by-block basis with pixel data stored in the frame buffer.

Abstract: A method and apparatus for controlling display of content signals begins by receiving a content signal that includes video content and at least one associated content control indicator. The content signal may also include audio content associated with the video content. The processing continues by comparing the at least one associated content control indicator (e.g., a rating of mature subject matter of the content signal) with at least one content control setting (e.g., a parental setting based on allowable viewing of rated content signals). When the associated content indicator compares unfavorably to the content control setting, a video graphics processor scrambles the at least a portion of the video content. The scrambled video content is then provided to a video rendering device for subsequent display.

Abstract: A video graphics system that includes a graphics processing circuit and a logic enhanced memory is presented. The logic enhanced memory includes an operation block that performs blending operations for fragment blocks received from the graphics processing circuit, where the fragment blocks include pixel fragments generated by rendering graphics primitives. In order to allow limited bandwidth buses that transport data between the graphics processing circuit and the logic enhanced memory to be used with maximum efficiency, an input buffer and an output buffer are included in the logic enhanced memory. A graphics processing circuit maintains history data that indicates how full the input and output buffers of the logic enhanced memory are, and as such, can ensure that new fragments blocks and operational commands are not provided to the logic enhanced memory in a manner that would cause the processing capabilities of the logic enhanced memory to be exceeded.

Abstract: A method and apparatus for managing compressed Z information in a video graphics system is described. Pixels in a display frame are grouped into a plurality of pixel blocks, where each pixel block includes a plurality of pixels. When possible, the Z information corresponding to the plurality of pixels in a pixel block is compressed and stored in a Z buffer in a compressed format. A Z mask value for each pixel block in the frame is stored in a Z mask memory, where the Z mask for each pixel block indicates a level of compression of the Z information for each of the pixel blocks. When Z information for a pixel block is required for processing operations, a cache is first examined to determine if the Z information for the pixel block is included in the cache. If the Z information is not included in the cache, the Z mask memory is consulted to determine the level of compression of the Z information for the particular pixel block.

Abstract: A method and apparatus for processing interrupts in a computing system include processing for ordering a plurality of interrupts for at least one processor. Such interrupts include system event interrupts, external device interrupts, and may further include power management interrupts, interprocessor interrupts, and/or intraprocessor interrupts. Such processing continues by generating an interrupt enable/disable signal based on the current context of a corresponding processor such that when the processor is performing a particular task which should not be interrupted, an interrupt signal is prevented from being provided to the processor. The processing also includes generating masking information to provide enable/disable masking information regarding each of the plurality of interrupts. As such, the computing system may enable/disable on a per interrupt basis the processing of a given interrupt.

Abstract: In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.

Abstract: A computation module and/or geometric engine for use in a video graphics processing circuit includes memory, a computation engine, a plurality of thread controllers, and an arbitration module. The computation engine is operably coupled to perform an operation based on an operation code and to provide a corresponding result to the memory as indicated by the operation code. Each of the plurality of thread controllers manages at least one corresponding thread of a plurality of threads. The plurality of threads constitutes an application. The arbitration module is coupled to the plurality of thread controllers and utilizes an application specific prioritization scheme to provide operation codes from the plurality of thread controllers to the computation engine such that idle time of the computation engine is minimized. The prioritization scheme prioritizes certain threads over other threads such that the throughput through the computation module is maximized.

Abstract: A method and apparatus for supporting shared microcode in a multi-thread computation engine is presented. Each of a plurality of thread controllers controls a thread of a plurality of threads that are included in the system. Rather than storing the operation codes associated with their respective threads and providing those operation codes to an arbitration module for execution, each of the thread controller stores operation code identifiers that are submitted to the arbitration module. Once the arbitration module has determine which operation code should be executed, it passes the operation code identifiers corresponding to that operation code to a microcode generation block. The microcode generation block uses the operation code identifiers to generate a set of input parameters that are provided to a computation engine for execution, where the input parameters correspond to those for the operation code encoded by the operation code identifiers received by the microcode generation block.

Abstract: A method and apparatus for combining a control signal and a video signal on a standard video cable is disclosed. The video cable is connected to a display monitor in order to provide access and control functions to the monitor. In a particular implementation, a USB signal is transmitted with a digital video signal across a standard digital video connector.