Abstract: A video processing device and method receives data from a common data source, such as a frame buffer and outputs first overlay information in a first color space from a first port and outputs second overlay information in a second color from a second port to facilitate output of multiple overlay images in different color spaces from common memory through different ports. In one embodiment a bidirectional port is used to allow a set of common signal pads or a bus to function as a flexible bidirectional video data port.

Abstract: A method and apparatus for providing a three-dimensional graphical user interface includes processing that begins by detecting selection of an information thumbnail of a plurality of information thumbnails. Note that the plurality of information thumbnails are presented on a display area that is at least a portion of a display. The processing then continues by retrieving detailed information based on the selected thumbnail. The process then continues by providing a three-dimensional object in a foreground viewing perspective to the plurality of information thumbnails. On at least some of the surfaces of the three-dimensional object, the retrieved detailed information is provided.

Abstract: A method and apparatus for motion compensation using a hardware-assisted abstraction layer is provided. A translator is added in the form of a set-up engine to convert graphics commands to a data structure compatible with a 3-D engine. By doing so, the 3-D engine may be used to serve the dual purposes of processing multiple types of graphics information, for example, 3-D graphics and MPEG video. As standards change and the 3-D engine is updated to accommodate new types of graphics information, the set-up engine may be modified to support the updated 3-D engine without requiring changes to drivers controlled by other entities.

Abstract: A computer system that performs motion compensation pixels, the computer system includes a storage device; a memory unit that loads at least one error correction value and at least one reference component into the storage device; and a calculation unit coupled to receive the at least one reference component and the at least one error correction value from the storage device. The calculation unit determines multiple predicted components in parallel and stores the multiple predicted components into the storage device. The arrangement, i.e., field or frame type, of the at least one reference component can differ from the arrangement of the stored multiple predicted components.

Abstract: A method and apparatus for controlling multiple displays from a drawing surface begins by obtaining a drawing surface setting that includes at least one of a refresh rate, resolution, and pixel depth. A user may select the drawing surface settings or are default parameters of the computer system. The processing continues by determining whether each of the multiple displays includes a display mode that substantially matches the drawing surface setting. If each of the multiple displays includes a display mode that matches the drawing surface setting, the images stored in the drawing surface are provided to the multiple displays based on the drawing surface setting. As such, the images will be displayed in full, without virtual desktop operation, unless selected by the user.

Abstract: A content addressable memory (CAM) has a CAM array and a CAM encoder. The CAM array in response to data stored in a memory address of the CAM array matching comparison data, produces a match signal corresponding to the memory address. The CAM encoder receives the match signal and using encoded cells, produces the memory address corresponding to the match signal.

Abstract: A method and apparatus for antialiasing in a video graphics system is presented. This is accomplished by determining if a pixel sample set, which results from oversampling, can be reduced to a compressed sample set that includes a single color value and a single Z value that fully describes a corresponding pixel. When the pixel sample set can be reduced to the compressed sample set, the compressed sample set is stored in a frame buffer at a location corresponding to the particular pixel that the sample set describes. When the pixel sample set cannot be reduced to a compressed sample set, pointer information is stored at the frame buffer location corresponding to the particular pixel. The pointer information includes a pointer that points to a selected address in a sample memory at which the complete sample set for the pixel is stored.

Abstract: A method and apparatus that extends the video graphics bus from the computer unit to a monitor is used within a computer system that includes a computer unit and a monitor. The computer unit includes a central processing unit, system memory, an accelerated graphics port chip set, and a first AGP coupling converter. The first AGP coupling converter is operably coupled to the AGP chip set and receives video graphics data (e.g., vertex data for triangles corresponding to three-dimensional graphics) and converts the transport formatting of the video graphics. Such transport formatting conversion may include changing from a parallel transport to a serial transport or from a parallel transport to a reduced parallel transport. The monitor includes a second AGP coupling converter, a video graphics controller, and a display device. The second AGP coupling converter is operably coupled, via a cable, to the first AGP coupling converter.

Abstract: A method and apparatus that includes processing for restricting usage of video signals in accordance with associated access restriction data begins by detecting the presence of the associated access restriction data as video signals are being received. The processing continues by interpreting usage instructions regarding the video signal. Such usage instructions may be requesting a digital copy of the video signals be made, sending the video signals to a television output, and/or sending a file of the digital video signal to another party via a file transfer. The processing continues by restricting usage of these video signals as requested by the usage instruction when prohibited by the associated access restriction data.

Abstract: A method and apparatus that reduce the complexity of motion estimation while providing better quality for a particular level of reduced resolution than previously available are described. The method and apparatus involve motion estimation quantization dithering to avoid quantization error effects when reducing the resolution, for example, from eight-bit pixel intensity values to two-bit pixel intensity values. Consequently, an embodiment of the invention provides efficient motion estimation using statistically accurate reduced resolution representations.

Abstract: A method and apparatus for handling an accessed bit in a page table entry is provided. When a page table entry is not present in a translation lookaside buffer (TLB), an electrical circuit causes a TLB miss exception and branching to a first software exception handler. The first software exception handler fetches the page table entry from main memory. The first software exception handler places the page table entry in the TLB. An electrical circuit determines whether an accessed bit of the page table entry has not been asserted. If the accessed bit is not asserted, an electrical circuit causes an accessed bit exception and branches execution to a second software exception handler. The second software exception handler asserts the accessed bit in the page table entry in main memory. The second software exception handler returns control back to the original memory access, causing execution to resume where it had left off prior to the TLB miss exception.

Abstract: A method and apparatus for generating a multimedia document that includes video image samples and associated audio is accomplished by decoding video signals into decoded video representations, sampling the decoded video representations at a rate below the motion video frame rate, and storing the video samples as a video document. For example, a JPEG (Joint picture expert group) document. In addition to creating video documents, the present method and apparatus also digitizes received audio signals and stores the digitized audio as an audio document. For example, as an AIFF (audio interchange file format audio format which is used with MAC OS™) audio document, a WAV (which is used with Windows™) audio document, or a RealAudio™ (which is the Internet standard for delivering continuous audio) audio document.

Abstract: A method and apparatus for providing live video on a three-dimensional object begins by receiving a video stream into a capture buffer. The process then continues by mapping, directly from the capture buffer, the video stream onto the three-dimensional object. Having mapped the live video onto the three-dimensional object it is rendered into a frame buffer and subsequently displayed on a display device.

Abstract: An approximation circuit approximates a function f(x) of an input value “x” by adding at least the first two terms in a Taylor series (i.e., f(a) and f′(a)(x−a)) where “a” is a number reasonably close to value “x”. The first term is generated by a first look-up table which receives the approximation value “a”. The first look-up table generates a function f(a) of the approximation value “a”. The second look-up table generates a first derivative f′(a) of the function f(a). A first multiplier then multiplies the first derivative f′(a) by a difference (x−a) between input value “x” and approximation value “a” to generate a product f′(a)(x−a). The approximation circuit can approximate the function f(x) by adding the third term of the Taylor series, (½)f″(a)(x−a)2.

Abstract: A FIFO memory device, FIFO control method and graphics processing system are disclosed which incorporate spread-spectrum EMI compensation. In one embodiment, a FIFO memory device and method includes generating a spread-spectrum adjustment signal for a spread-spectrum FIFO based on an address offset associated with a read and write address associated with a spread-spectrum FIFO. The method includes adjusting the spread-spectrum clock signal in response to the spread-spectrum adjustment signal based on the address offset associated with the read and write address. A spread-spectrum FIFO receives data from a data source, such as a graphics data source, which may include a memory such as a RAMDAC. The data can be provided by a display engine or other suitable information provider.

Abstract: A branch resolution logic for an in-order processor is provided which scans the stages of processor pipeline to determine the oldest branch instruction having sufficient condition codes for resolution. The stages are scanned in order from the latter stages to the earlier stages, which allows quick and simple branch resolution. Therefore, because branches are resolved as soon as the necessary condition codes are generated in a specific stage, branch mispredict penalties are minimized.

Abstract: A method for assuring that samples are always available for transmission when a modern is implemented as a process executing in the memory of a host computer. The modem process converts, digital information into transmit data samples. In the absence of digital information, the modem process converts fill data into fill data samples. The transmit data samples and fill data samples are stored in a segmented buffer for transmission to a remote modem. If additional transmit data samples become available and the buffer contains fill data samples which have not been transmitted to the remote modem, the modem process replaces the fill data samples in the buffer with the additional transmit data samples. The method helps assure that samples are always available for transmission, and simultaneously reduces the time delay or latency between when data enter the modem and when the data are subsequently transmitted.

Abstract: A method and apparatus for processing interrupts in a computing system include processing for ordering a plurality of interrupts for at least one processor. Such interrupts include system event interrupts, external device interrupts, and may further include power management interrupts, interprocessor interrupts, and/or intraprocessor interrupts. Such processing continues by generating an interrupt enable/disable signal based on the current context of a corresponding processor such that when the processor is performing a particular task which should not be interrupted, an interrupt signal is prevented from being provided to the processor. The processing also includes generating masking information to provide enable/disable masking information regarding each of the plurality of interrupts. As such, the computing system may enable/disable on a per interrupt basis the processing of a given interrupt.

Abstract: In accordance with an embodiment of the present invention a digital representation of a YCbCr video signal data stream is received that represents a video image or a series of video images. Received Y data values are linearly transformed and used to provide an RGB signal. The RGB signal is non-linearly adjusted to provide an adjusted RGB signal that enhances the viewed brightness of the data. In a specific embodiment, the non-linear adjusting adjusts the brightness of data near a mid-range of the video image more than other ranges of data.

Abstract: A lighting effect computation block and method therefore is presented. The lighting effect computation block separates lighting effect calculations for video graphics primitives into a number of simpler calculations that are performed in parallel but accumulated in an order-dependent manner. Each of the individual calculations is managed by a separate thread controller, where lighting effect calculations for a vertex of a primitive may be performed using a single parent light thread controller and a number of sub-light thread controllers. Each thread controller manages a thread of operation codes related to determination of the lighting parameters for the particular vertex. The thread controllers submit operation codes to an arbitration module based on the expected latency and interdependency between the various operation codes. The arbitration module determines which operation code is executed during a particular cycle, and provides that operation code to a computation engine.