Abstract: An example method comprises receiving, by a first PHY of a first transceiver, a timing packet, timestamping, by the first transceiver, the timing packet and providing the timing packet to a first intermediate node, determining a first offset between the first intermediate node and the first transceiver, updating a first field within the timing packet with the first offset between the first intermediate node and the first transceiver, the offset being in the direction of the second transceiver, receiving the timing packet by a second transceiver, the timing packet including the first field, information within the first field being at least based on the first offset, determining a second offset between the second transceiver and an intermediate node that provided the timing packet to the second transceiver and correcting a time of the second transceiver based on the information within the first field and the second offset.

Abstract: An example system comprises a first antenna and a modem. The first antenna is configured to receive a signal from a transmitting radio frequency unit. The signal includes data and a known sequence. The modem is configured to retrieve the known sequence from the signal, transform the known sequence and the data into a frequency domain, calculate averages of groups of neighboring frequency points in the frequency domain to reduce the effect of nonlinear noise in the signal, the neighboring frequency points corresponding to the preamble in the frequency domain, compare the calculated averages to an expected frequency response in the frequency domain, determine a correction filter to apply to the data based on the comparison, apply the correction filter on the data in the frequency domain to create corrected data, transform the corrected data from the frequency domain to the time domain, and provide the data.

Abstract: Systems and methods for combining signals from multiple active wireless receivers are discussed herein. An exemplary system comprises a first downconverter, a phase comparator, a phase adjuster, and a second downconverter. The first downconverter may be configured to downconvert a received signal from a first antenna to an intermediate frequency to create an intermediate frequency signal. The phase comparator may be configured to mix the received signal and a downconverted signal to create a mixed signal, compare a phase of the mixed signal to a predetermined phase, and generate a phase control signal based on the comparison, the downconverted signal being associated with the received signal from the first antenna. The phase adjuster may be configured to alter the phase of the intermediate frequency signal based on the phase control signal. The second downconverter may be configured to downconvert the phase-shifted intermediate frequency signal to create an output signal.

Abstract: A frame error correction circuit may identify and correct errors in data frames provided to a receiver as part of a diversity communications scheme. The frame error correction circuit may further align the data frames so that the data frames can be compared. The frame error correction circuit may perform a bit-wise comparison of the data frames and identify inconsistent bit positions where bits in the data frames differ from one another. Once inconsistent bit positions have been identified, the frame error correction circuit may access a permutation table of permutations of bits at the inconsistent bit positions. In some implementations, the frame error correction circuit uses the permutation table to reassemble permutations of the data frames. In various implementations, the frame error correction circuit performs a CRC of each permutation of the data frames, and provides a valid permutation to a network.

Abstract: Rapid failure detection and recovery in wireless communication networks is needed in order to meet, among other things, carrier class Ethernet transport channel standards. Thus, resilient wireless packet communications is provided using a hardware-assisted rapid transport channel failure detection algorithm and a Gigabit Ethernet data access card with an engine configured accordingly. In networks with various topologies, this is provided in combination with their existing protocols, such as rapid spanning tree and link aggregation protocols, respectively.

Abstract: Various embodiments provide for systems, methods, or apparatuses that provide a fronthaul architecture that facilitates high fidelity and low latency communication between a radio processing unit, such as a baseband unit (BBU), which may be located a central office (CO), and a remote transceiver, which may comprise a remote radio head (RRH) or a remote radio unit (RRU), which may be located at remote cell site.

Abstract: An exemplary system comprises a linearizer module, a first upconverter module, a power amplifier module, a signal sampler module, and a downconverter module. The linearizer module may be configured to receive a first intermediate frequency signal and to adjust the first intermediate frequency signal based on a reference signal and a signal based on a second intermediate frequency signal. The first upconverter module may be configured to receive and up-convert a signal based on the adjusted first intermediate frequency signal to a radio frequency signal. The power amplifier module may be configured to receive and amplify a power of a signal based on the radio frequency signal. The signal sampler module may be configured to sample a signal based on the amplified radio frequency signal. The downconverter module may be configured to receive and down-convert a signal based on the sampled radio frequency signal to the second intermediate frequency signal.

Abstract: Systems and methods for improved chip device performance are discussed herein. An exemplary chip device for use in an integrated circuit comprises a bottom and a top opposite the bottom. The chip device comprises a through-chip device interconnect and a clearance region. The through-chip device interconnect is configured to provide an electrical connection between a ground plane trace on the bottom and a chip device path on the top of the chip device. The clearance region on the bottom of the chip device comprises an electrically conductive substance. The size and shape of the clearance region assist in impedance matching. The chip device path on the top of the chip device may further comprise at least one tuning stub. The size and shape of the at least one tuning stub also assist in impedance matching.

Abstract: A system comprises a wheel assembly including a wheel shaft and first and second wheels rotationally coupled to the wheel shaft; a first bracket coupled to a device rack and including a first open slot, the first open slot including a receiving portion configured to receive the wheel shaft at a first position, a delivery portion configured to deliver the wheel shaft upon tilting the rack forwards, and a locking portion configured to secure the wheel shaft upon tilting the rack backwards; and a second bracket configured to be coupled to the rack on a second side and including a second open slot, the second open slot including a receiving portion configured to receive the wheel shaft at a second position, a delivery portion configured to deliver the wheel shaft upon tilting the rack forwards, and a locking portion configured to secure the wheel shaft upon tilting the rack backwards.

Abstract: An example method comprises receiving, by a first PHY of a first transceiver, a timing packet, timestamping, by the first transceiver, the timing packet and providing the timing packet to a first intermediate node, determining a first offset between the first intermediate node and the first transceiver, updating a first field within the timing packet with the first offset between the first intermediate node and the first transceiver, the offset being in the direction of the second transceiver, receiving the timing packet by a second transceiver, the timing packet including the first field, information within the first field being at least based on the first offset, determining a second offset between the second transceiver and an intermediate node that provided the timing packet to the second transceiver and correcting a time of the second transceiver based on the information within the first field and the second offset.

Abstract: A system comprises a wheel assembly including a wheel shaft and first and second wheels rotationally coupled to the wheel shaft; a first bracket coupled to a device rack and including a first open slot, the first open slot including a receiving portion configured to receive the wheel shaft at a first position, a delivery portion configured to deliver the wheel shaft upon tilting the rack forwards, and a locking portion configured to secure the wheel shaft upon tilting the rack backwards; and a second bracket configured to be coupled to the rack on a second side and including a second open slot, the second open slot including a receiving portion configured to receive the wheel shaft at a second position, a delivery portion configured to deliver the wheel shaft upon tilting the rack forwards, and a locking portion configured to secure the wheel shaft upon tilting the rack backwards.

Abstract: An example system comprises a first antenna and a modem. The first antenna is configured to receive a signal from a transmitting radio frequency unit. The signal includes data and a known sequence. The modem is configured to retrieve the known sequence from the signal, transform the known sequence and the data into a frequency domain, calculate averages of groups of neighboring frequency points in the frequency domain to reduce the effect of nonlinear noise in the signal, the neighboring frequency points corresponding to the preamble in the frequency domain, compare the calculated averages to an expected frequency response in the frequency domain, determine a correction filter to apply to the data based on the comparison, apply the correction filter on the data in the frequency domain to create corrected data, transform the corrected data from the frequency domain to the time domain, and provide the data.

Abstract: A frame error correction circuit may identify and correct errors in data frames provided to a receiver as part of a diversity communications scheme. The frame error correction circuit may further align the data frames so that the data frames can be compared. The frame error correction circuit may perform a bit-wise comparison of the data frames and identify inconsistent bit positions where bits in the data frames differ from one another. Once inconsistent bit positions have been identified, the frame error correction circuit may access a permutation table of permutations of bits at the inconsistent bit positions. In some implementations, the frame error correction circuit uses the permutation table to reassemble permutations of the data frames. In various implementations, the frame error correction circuit performs a CRC of each permutation of the data frames, and provides a valid permutation to a network.

Abstract: An example system comprises a router configured to receive a bandwidth update associated with a change in bandwidth over a wireless channel, determine if the change in bandwidth identified in the bandwidth update results in bandwidth being over-reserved at at least one priority level, previously reserved bandwidth of the wireless channel being associated with a plurality of different priority levels, the previously reserved bandwidth being previously reserved based on a plurality of path requests from a head end router, each path request including at least one priority level and a bandwidth reservation request, if the change in bandwidth results in bandwidth being over-reserved, then preempt a lowest priority path request, based in the preemption of the lowest priority path request, update reserved bandwidth of the wireless channel of at least one priority level, and provide a message to the head end router regarding the change of bandwidth.

Abstract: Rapid failure detection and recovery in wireless communication networks is needed in order to meet, among other things, carrier class Ethernet transport channel standards. Thus, resilient wireless packet communications is provided using a hardware-assisted rapid transport channel failure detection algorithm and a Gigabit Ethernet data access card with an engine configured accordingly. In networks with various topologies, this is provided in combination with their existing protocols, such as rapid spanning tree and link aggregation protocols, respectively.

Abstract: An example system comprising a first transceiver configured to receive a request airframe from a second transceiver over a wireless link, the request airframe including a first timestamp indicating a first time T1 timestamp a second time indication indicating a second time T2 that the request airframe was received, generate a respond airframe and including a third time indication indicating a third time T3 that the respond airframe is transmitted to the second transceiver, transmit the respond airframe to the second transceiver, provide a timestamp information request to second transceiver, receive a timestamp information response, the timestamp information response including a fourth time indication indicating a fourth time T4, calculate a counter offset using the first time, second time, third time and fourth time as follows: counter ? ? offset = ( TS ? ? 1 + TS ? ? 4 - TS ? ? 3 - TS ? ? 2 ) 2 , calculate a phase offset based on the counter offset, and correct a phas

Abstract: An example method comprises receiving, by a first PHY of a first transceiver, a timing packet, timestamping, by the first transceiver, the timing packet and providing the timing packet to a first intermediate node, determining a first offset between the first intermediate node and the first transceiver, updating a first field within the timing packet with the first offset between the first intermediate node and the first transceiver, the offset being in the direction of the second transceiver, receiving the timing packet by a second transceiver, the timing packet including the first field, information within the first field being at least based on the first offset, determining a second offset between the second transceiver and an intermediate node that provided the timing packet to the second transceiver and correcting a time of the second transceiver based on the information within the first field and the second offset.

Abstract: A first layer one link aggregation master comprises a first port coupled to receive customer traffic; a first channel; a second channel; an aggregation engine coupled to the first and second channels; a first switch circuit coupled to the first port and to the first channel, and configured to communicate the customer traffic from the first port over the first channel to the aggregation engine, the aggregation engine including a splitter circuit configured to use layer one information to segment at least a portion of the customer traffic into a first virtual container and a second virtual container, the aggregation engine further including an encapsulation circuit configured to encapsulate the second virtual container using Ethernet standards for transport over the second channel; a radio access card configured to generate an air frame based on the first virtual container for wireless transmission over a first wireless link of a link aggregation group to the receiver; and a second switch circuit coupled to the

Abstract: A first layer one link aggregation master comprises a first port coupled to receive customer traffic; a first channel; a second channel; an aggregation engine coupled to the first and second channels; a first switch circuit coupled to the first port and to the first channel, and configured to communicate the customer traffic from the first port over the first channel to the aggregation engine, the aggregation engine including a splitter circuit configured to use layer one information to segment at least a portion of the customer traffic into a first virtual container and a second virtual container, the aggregation engine further including an encapsulation circuit configured to encapsulate the second virtual container using Ethernet standards for transport over the second channel; a radio access card configured to generate an air frame based on the first virtual container for wireless transmission over a first wireless link of a link aggregation group to the receiver; and a second switch circuit coupled to the

Abstract: An example system comprises a first antenna and a modem. The first antenna is configured to receive a signal from a transmitting radio frequency unit. The signal includes data and a known sequence. The modem is configured to retrieve the known sequence from the signal, transform the known sequence and the data into a frequency domain, calculate averages of groups of neighboring frequency points in the frequency domain to reduce the effect of nonlinear noise in the signal, the neighboring frequency points corresponding to the preamble in the frequency domain, compare the calculated averages to an expected frequency response in the frequency domain, determine a correction filter to apply to the data based on the comparison, apply the correction filter on the data in the frequency domain to create corrected data, transform the corrected data from the frequency domain to the time domain, and provide the data.