Abstract: A frame error correction circuit may identify and correct errors in data frames provided to a receiver as part of a diversity communications scheme. The frame error correction circuit may further align the data frames so that the data frames can be compared. The frame error correction circuit may perform a bit-wise comparison of the data frames and identify inconsistent bit positions where bits in the data frames differ from one another. Once inconsistent bit positions have been identified, the frame error correction circuit may access a permutation table of permutations of bits at the inconsistent bit positions. In some implementations, the frame error correction circuit uses the permutation table to reassemble permutations of the data frames. In various implementations, the frame error correction circuit performs a CRC of each permutation of the data frames, and provides a valid permutation to a network.

Abstract: Various embodiments provide for systems, methods, or apparatuses that provide a fronthaul architecture that facilitates high fidelity and low latency communication between a radio processing unit, such as a baseband unit (BBU), which may be located a central office (CO), and a remote transceiver, which may comprise a remote radio head (RRH) or a remote radio unit (RRU), which may be located at remote cell site.

Abstract: Various embodiments provide for systems and methods for signal conversion of one modulated signal to another modulated signal using demodulation and then re-modulation. According to some embodiments, a signal receiving system may comprise an I/Q demodulator that demodulates a first modulated signal to an in-phase (“I”) signal and a quadrature (“Q”) signal, an I/Q signal adjustor that adaptively adjusts the Q signal to increase the signal-to-noise ratio (SNR) of a transitory signal that is based on a second modulated signal, and an I/Q modulator that modulates the I signal and the adjusted Q signal to the second modulated signal. To increase the SNR, the Q signal may be adjusted based on a calculated error determined for the transitory signal during demodulation by a demodulator downstream from the I/Q modulator.

Abstract: Rapid failure detection and recovery in wireless communication networks is needed in order to meet, among other things, carrier class Ethernet transport channel standards. Thus, resilient wireless packet communications is provided using a hardware-assisted rapid transport channel failure detection algorithm and a Gigabit Ethernet data access card with an engine configured accordingly. In networks with various topologies, this is provided in combination with their existing protocols, such as rapid spanning tree and link aggregation protocols, respectively.

Abstract: Various embodiments provide for waveguide assemblies which may be utilized in wireless communication systems. Various embodiments may allow for waveguide assemblies to be assembled using tools and methodologies that are simpler than the conventional alternatives. Some embodiments provide for a waveguide assembly that comprises a straight tubular portion configured to be shortened, using simple techniques and tools, in order to fit into a waveguide assembly. For instance, for some embodiments, the waveguide assembly may be configured such that the straight portion can be shortened, at a cross section of the portion, using a basic cutting tool, such a hacksaw. In some embodiments, the straight portion may be further configured such that regardless of whether the straight tubular portion is shortened, the waveguide assembly remains capable of coupling to flanges, which facilitate coupling the straight tubular portion to connectable assemblies, such as other waveguide assemblies, radio equipment, or antennas.

Abstract: A first layer one link aggregation master comprises a first port coupled to receive customer traffic; a first channel; a second channel; an aggregation engine coupled to the first and second channels; a first switch circuit coupled to the first port and to the first channel, and configured to communicate the customer traffic from the first port over the first channel to the aggregation engine, the aggregation engine including a splitter circuit configured to use layer one information to segment at least a portion of the customer traffic into a first virtual container and a second virtual container, the aggregation engine further including an encapsulation circuit configured to encapsulate the second virtual container using Ethernet standards for transport over the second channel; a radio access card configured to generate an air frame based on the first virtual container for wireless transmission over a first wireless link of a link aggregation group to the receiver; and a second switch circuit coupled to the

Abstract: An exemplary method comprises positioning a first antenna to receive a first signal from a second antenna, the second antenna comprising energy absorbing material that functions to expand beamwidth, receiving the first signal from the second antenna, detecting a plurality of gains based on the first signal, repositioning the first antenna relative to the second antenna to a position associated with an acceptable gain based on the first signal, removing at least some of the energy absorbing material from the second antenna to narrow the beamwidth of the second antenna, receiving, by the first antenna, a second signal from the second antenna, detecting a plurality of gains based on the second signal, and repositioning the first antenna relative to the second antenna to a position associated with an increased gain of the plurality of gains based on the second signal, the increased gain being greater than the acceptable gain.

Abstract: An exemplary method of synchronizing a master clock and a slave clock comprises transmitting a plurality of packets between a master device and a slave device, calculating a first skew between a first pair of the plurality of packets at the slave device and a second skew between the first pair at the master device, calculating a ratio between the first skew and the second skew, providing a slave clock frequency correction to the slave device, calculating a first packet trip delay using a time that the master device initiates sending a packet to the slave device, a time the master device receives a response from the slave device, a corrected time the slave device receives the packet, and a corrected time the slave device initiates sending the response, calculating a first offset based on the first packet trip delay, and providing the first offset to the slave device.

Abstract: An exemplary method of synchronizing a master clock and a slave clock comprises transmitting a plurality of packets between a master device and a slave device, calculating a first skew between a first pair of the plurality of packets at the slave device and a second skew between the first pair at the master device, calculating a ratio between the first skew and the second skew, providing a slave clock frequency correction to the slave device, calculating a first packet trip delay using a time that the master device initiates sending a packet to the slave device, a time the master device receives a response from the slave device, a corrected time the slave device receives the packet, and a corrected time the slave device initiates sending the response, calculating a first offset based on the first packet trip delay, and providing the first offset to the slave device.

Abstract: Various embodiments provide for systems and methods for signal conversion of one modulated signal to another modulated signal using demodulation and then re-modulation. According to some embodiments, a signal receiving system may comprise an I/Q demodulator that demodulates a first modulated signal to an in-phase (“I”) signal and a quadrature (“Q”) signal, an I/Q signal adjustor that adaptively adjusts the Q signal to increase the signal-to-noise ratio (SNR) of a transitory signal that is based on a second modulated signal, and an I/Q modulator that modulates the I signal and the adjusted Q signal to the second modulated signal. To increase the SNR, the Q signal may be adjusted based on a calculated error determined for the transitory signal during demodulation by a demodulator downstream from the I/Q modulator.

Abstract: Rapid failure detection and recovery in wireless communication networks is needed in order to meet, among other things, carrier class Ethernet transport channel standards. Thus, resilient wireless packet communications is provided using a hardware-assisted rapid transport channel failure detection algorithm and a Gigabit Ethernet data access card with an engine configured accordingly. In networks with various topologies, this is provided in combination with their existing protocols, such as rapid spanning tree and link aggregation protocols, respectively.

Abstract: An exemplary system comprises a linearizer module, a first upconverter module, a power amplifier module, a signal sampler module, and a downconverter module. The linearizer module may be configured to receive a first intermediate frequency signal and to adjust the first intermediate frequency signal based on a reference signal and a signal based on a second intermediate frequency signal. The first upconverter module may be configured to receive and up-convert a signal based on the adjusted first intermediate frequency signal to a radio frequency signal. The power amplifier module may be configured to receive and amplify a power of a signal based on the radio frequency signal. The signal sampler module may be configured to sample a signal based on the amplified radio frequency signal. The downconverter module may be configured to receive and down-convert a signal based on the sampled radio frequency signal to the second intermediate frequency signal.

Abstract: Various embodiments provide for systems, methods, or apparatuses that provide a fronthaul architecture that facilitates high fidelity and low latency communication between a radio processing unit, such as a baseband unit (BBU), which may be located a central office (CO), and a remote transceiver, which may comprise a remote radio head (RRH) or a remote radio unit (RRU), which may be located at remote cell site.

Abstract: An exemplary method of synchronizing a master clock and a slave clock comprises transmitting a plurality of packets between a master device and a slave device, calculating a first skew between a first pair of the plurality of packets at the slave device and a second skew between the first pair at the master device, calculating a ratio between the first skew and the second skew, providing a slave clock frequency correction to the slave device, calculating a first packet trip delay using a time that the master device initiates sending a packet to the slave device, a time the master device receives a response from the slave device, a corrected time the slave device receives the packet, and a corrected time the slave device initiates sending the response, calculating a first offset based on the first packet trip delay, and providing the first offset to the slave device.

Abstract: Various embodiments provide for systems and methods of backhaul optimization. An exemplary system comprises a plurality of low power cells and a connector node. The connector node may be in communication with the plurality of low power cells. The connector node may be configured to receive demands from each of the plurality of low power cells. Each of the demands may indicate a demand at a predetermined time. The connector node may be further configured to determine a rate for each of the plurality of low power cells based on the demands of each of the low power cells and the assigned rate of the other of the plurality of low power cells. The connector node may be further configured to allocate capacity based on the determined rates.

Abstract: An exemplary system comprises a linearizer module, a first upconverter module, a power amplifier module, a signal sampler module, and a downconverter module. The linearizer module may be configured to receive a first intermediate frequency signal and to adjust the first intermediate frequency signal based on a reference signal and a signal based on a second intermediate frequency signal. The first upconverter module may be configured to receive and up-convert a signal based on the adjusted first intermediate frequency signal to a radio frequency signal. The power amplifier module may be configured to receive and amplify a power of a signal based on the radio frequency signal. The signal sampler module may be configured to sample a signal based on the amplified radio frequency signal. The downconverter module may be configured to receive and down-convert a signal based on the sampled radio frequency signal to the second intermediate frequency signal.

Abstract: Systems and methods for improved chip device performance are discussed herein. An exemplary chip device for use in an integrated circuit comprises a bottom and a top opposite the bottom. The chip device comprises a through-chip device interconnect and a clearance region. The through-chip device interconnect is configured to provide an electrical connection between a ground plane trace on the bottom and a chip device path on the top of the chip device. The clearance region on the bottom of the chip device comprises an electrically conductive substance. The size and shape of the clearance region assist in impedance matching. The chip device path on the top of the chip device may further comprise at least one tuning stub. The size and shape of the at least one tuning stub also assist in impedance matching.

Abstract: An example system comprises a first antenna and a modem. The first antenna is configured to receive a signal from a transmitting radio frequency unit. The signal includes data and a known sequence. The modem is configured to retrieve the known sequence from the signal, transform the known sequence and the data into a frequency domain, calculate averages of groups of neighboring frequency points in the frequency domain to reduce the effect of nonlinear noise in the signal, the neighboring frequency points corresponding to the preamble in the frequency domain, compare the calculated averages to an expected frequency response in the frequency domain, determine a correction filter to apply to the data based on the comparison, apply the correction filter on the data in the frequency domain to create corrected data, transform the corrected data from the frequency domain to the time domain, and provide the data.

Abstract: A frame error correction circuit may identify and correct errors in data frames provided to a receiver as part of a diversity communications scheme. The frame error correction circuit may further align the data frames so that the data frames can be compared. The frame error correction circuit may perform a bit-wise comparison of the data frames and identify inconsistent bit positions where bits in the data frames differ from one another. Once inconsistent bit positions have been identified, the frame error correction circuit may access a permutation table of permutations of bits at the inconsistent bit positions. In some implementations, the frame error correction circuit uses the permutation table to reassemble permutations of the data frames. In various implementations, the frame error correction circuit performs a CRC of each permutation of the data frames, and provides a valid permutation to a network.

Abstract: Systems and methods for improved chip device performance are discussed herein. An exemplary chip device for use in an integrated circuit comprises a bottom and a top opposite the bottom. The chip device comprises a through-chip device interconnect and a clearance region. The through-chip device interconnect is configured to provide an electrical connection between a ground plane trace on the bottom and a chip device path on the top of the chip device. The clearance region on the bottom of the chip device comprises an electrically conductive substance. The size and shape of the clearance region assists in impedance matching. The chip device path on the top of the chip device may further comprise at least one tuning stub. The size and shape of the at least one tuning stub also assists in impedance matching.