Abstract: A III-V semiconductor pixel X-ray detector, including an absorption region of a first or a second conductivity type, at least nine semiconductor contact regions of the second conductivity type arranged in a matrix along the upper side of the absorption region, and optionally a semiconductor contact layer of the first conductivity type, a metallic front side connecting contact being arranged beneath the absorption region, and a metallic rear side connecting contact being arranged above each semiconductor contact region, and a semiconductor passivation layer of the first or the second conductivity type. The semiconductor passivation layer and the absorption region being lattice-matched to each other. The semiconductor passivation layer being arranged in regions on the upper side of the absorption region. The semiconductor passivation layer having a minimum distance of at least 2 ?m or at least 20 ?m with respect to each highly doped semiconductor contact region.

Abstract: A monolithic multi-junction solar cell comprising a first III-V subcell and a second III-V subcell and a third III-V subcell and a fourth Ge subcell, wherein the subcells are stacked on top of one another in the specified order, and the first subcell forms the top subcell and a metamorphic buffer is formed between the third subcell and the fourth subcell and all subcells each have an n-doped emitter layer and a p-doped base layer and the emitter doping in the second subcell is lower than the base doping.

Abstract: A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 ?m2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Abstract: A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 ?m2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Abstract: A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 ?m2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Abstract: A vertical high-blocking III-V bipolar transistor, which includes an emitter, a base and a collector. The emitter has a highly doped emitter semiconductor contact region of a first conductivity type and a first lattice constant. The base has a low-doped base semiconductor region of a second conductivity type and the first lattice constant. The collector has a layered low-doped collector semiconductor region of the first conductivity type with a layer thickness greater than 10 ?m and the first lattice constant. The collector has a layered highly doped collector semiconductor contact region of the first conductivity type. A first metallic connecting contact layer is formed in regions being integrally connected to the emitter. A second metallic connecting contact layer is formed in regions being integrally connected to the base. A third metallic connecting contact region is formed at least in regions being arranged beneath the collector.

Abstract: A stacked monolithic multi-junction solar cell having at least four subcells, wherein the band gap increases starting from the first subcell in the direction of the fourth subcell, each subcell has an n-doped emitter and a p-doped base, the emitter and the base of the first subcell each are formed of germanium, all following subcells each have at least one element of main group III and V of the periodic table, all subcells following the first subcell are formed lattice-matched to one another, a semiconductor mirror having a plurality of doped semiconductor layers with alternately different refractive indices is placed between the first and second subcell, the semiconductor layers of the semiconductor mirror are each formed n-doped and each have a dopant concentration of at most 5·1018 cm?3, the semiconductor mirror is placed between the first subcell and the first tunnel diode.

Abstract: A semiconductor layer stack, a component made therefrom, a component module, and a production method is provided. The semiconductor layer stack has at least two layers (A, B), which, as individual layers, each have an energy position of the Fermi level in the semiconductor band gap, E F - E V < E G 2 applying to the layer (A) and E L - E F < E G 2 applying to the layer (B), with EF the energy position of the Fermi level, EV the energy position of the valence band, EL the energy position of a conduction band and EL?EV the energy difference of the semiconductor band gap EG, the thickness of the layers (A, B) being selected in such a way that a continuous space charge zone region over the layers (A, B) results.

Abstract: A solar cell contact arrangement, having a semiconductor body with a top and a bottom, wherein the semiconductor body has multiple solar cell stacks and includes a support substrate on the bottom, and each solar cell stack has at least two III-V subcells arranged on the support substrate and at least one through-contact extending from the top to the bottom of the semiconductor body with a continuous side wall, wherein the through-contact has a first edge region on the top and a second edge region on the bottom, and the first edge region has a first section and a second, metallic section, and the second edge region has a first section and a second section, wherein the respective second sections completely enclose the respective first sections, and an insulating layer.

Abstract: A method for plating by means of a through-hole on a semiconductor wafer at least comprising the steps: providing a semiconductor wafer having a top side and a bottom side, wherein the semiconductor wafer has a plurality of solar cell stacks and comprises a substrate on the bottom side, and each solar cell stack has at least two III-V subcells, disposed on the substrate, and at least one through-hole, extending from the top side to the bottom side of the semiconductor wafer, with a continuous side wall, wherein the through-hole has a first edge region on the top side and a second edge region on the bottom side; applying an insulating layer to part of the first edge region, the side wall, and to the second edge region by means of a first printing process; and applying an electrically conductive layer.

Abstract: A semiconductor layer stack, a component made therefrom, a component module, and a production method is provided. The semiconductor layer stack has at least two layers (A, B), which, as individual layers, each have an energy position of the Fermi level in the semiconductor band gap, E F - E V < E G 2 applying to the layer (A) and E L - E F < E G 2 applying to the layer (B), with EF the energy position of the Fermi level, EV the energy position of the valence band, EL the energy position of a conduction band and EL?EV the energy difference of the semiconductor band gap EG, the thickness of the layers (A, B) being selected in such a way that a continuous space charge zone region over the layers (A, B) results.

Abstract: A method for structuring an insulating layer on a semiconductor wafer, at least comprising the steps of: Provision of a semiconductor wafer with a top, a bottom and comprising multiple solar cell stacks, wherein each solar cell stack is a Ge substrate, which forms the bottom of the semiconductor wafer, a Ge subcell and at least two III-V subcells, in the above order, and at least one passage opening, which extends from the top to the bottom of the semiconductor wafer and has a connected side wall, an insulating layer two-dimensionally deposited on the top of the semiconductor wafer, on the side wall of the passage opening and/or on the bottom of the semiconductor wafer, and the deposition of an etch-resistant filling material by means of a printing process on an area of the top which comprises the passage opening, and into the passage opening.

Abstract: A stacked III-V semiconductor diode comprising or consisting of GaAs, with a heavily n-doped cathode layer, a heavily p-doped anode layer, and a drift region arranged between the cathode layer and the anode layer with a dopant concentration of at most 8·1015 cm?3, and a layer thickness of at least 10 ?m, wherein the cathode layer has a delta layer section with a layer thickness of 0.1 ?m to 2 ?m and a dopant concentration of at least 1·1019 cm?3.

Abstract: A dicing method for separating a wafer comprising a plurality of solar cells stack along at least one parting line, at least having the steps of: providing the wafer with a top, a bottom, an adhesive layer which is integrally bonded with the top and a cover glass layer which is integrally bonded with the adhesive layer, wherein the wafer includes a plurality of solar cell stacks, each having a germanium substrate layer forming the bottom of the wafer, a germanium sub-cell and at least two III-V sub-cells; creating a separating trench along the parting line by means of laser ablation, which extends from a bottom of the wafer through the wafer and the adhesive layer at least up to a top of the cover glass layer; and dividing the cover glass layer along the separating trench.

Abstract: A monolithic metamorphic multi-junction solar cell comprising a first III-V subcell and a second III-V subcell and a third III-V subcell and a fourth Ge subcell, wherein the subcells are stacked on top of each other in the indicated order, and the first subcell forms the topmost subcell, and a metamorphic buffer is formed between the third subcell and the fourth subcell and all subcells each have an n-doped emitter layer and a p-doped base layer, and the emitter layer of the second subcell is greater than the base layer.

Abstract: A solar cell stack includes a first semiconductor solar cell having a p-n junction made of a first material with a first lattice constant, a second semiconductor solar cell having a p-n junction made of a second material with a second lattice constant, and the first lattice constant being at least 0.008 ? smaller than the second lattice constant, and a metamorphic buffer. The metamorphic buffer is formed between the first semiconductor solar cell and the second semiconductor solar cell. The metamorphic buffer includes a series of at least five layers. The lattice constant increases in the series in the direction of the semiconductor solar cell. The lattice constants of the layers of the metamorphic buffer are larger than the first lattice constant. Two layers of the buffer having a doping and the difference in the dopant concentration between the two layers being greater than 4E17 cm?3.

Abstract: A monolithic multiple solar cell includes at least three partial cells, with a semiconductor mirror placed between two partial cells. The aim of the invention is to improve the radiation stability of said solar cell. For this purpose, the semiconductor mirror has a high degree of reflection in at least one part of a spectral absorption area of the partial cell which is arranged above the semiconductor mirror and a high degree of transmission within the spectral absorption range of the partial cell arranged below the semiconductor mirror.

Abstract: A stacked, high-blocking III-V semiconductor power diode having a first metallic terminal contact layer, formed at least in regions, and a highly doped semiconductor contact region of a first conductivity type and a first lattice constant. A drift layer of a second conductivity type and having a first lattice constant is furthermore provided. A semiconductor contact layer of a second conductivity, which includes an upper side and an underside, and a second metallic terminal contact layer are formed, and the second metallic terminal contact layer being integrally connected to the underside of the semiconductor contact layer, and the semiconductor contact layer having a second lattice constant at least on the underside, and the second lattice constant being the lattice constant of InP, and the drift layer and the highly doped semiconductor contact region each comprising an InGaAs compound or being made up of InGaAs.

Abstract: A stacked multi-junction solar cell with a metallization comprising a multilayer system, wherein the multi-junction solar cell has a germanium substrate forming a bottom side of the multi-junction solar cell, a germanium subcell, and at least two III-V subcells, the multilayer system of the metallization has a first layer, comprising gold and germanium, a second layer comprising titanium, a third layer, comprising palladium or nickel or platinum, with a layer thickness, and at least one metallic fourth layer, and the multilayer system of the metallization covers at least one first and second surface section and is integrally connected to the first and second surface section, wherein the first surface section is formed by the dielectric insulation layer and the second surface section is formed by the germanium substrate or by a III-V layer.

Abstract: A stacked high barrier III-V power semiconductor diode having an at least regionally formed first metallic terminal contact layer and a heavily doped semiconductor contact region of a first conductivity type with a first lattice constant, a drift layer of a second conductivity type, a heavily doped metamorphic buffer layer sequence of the second conductivity type is formed. The metamorphic buffer layer sequence has an upper side with the first lattice constant and a lower side with a second lattice constant. The first lattice constant is greater than the second lattice constant. The upper side of the metamorphic buffer layer sequence is arranged in the direction of the drift layer. A second metallic terminal contact layer is arranged below the lower side of the metamorphic buffer layer sequence. The second metallic terminal contact layer is integrally bonded with a semiconductor contact layer.