Patents Assigned to Azur Space Solar Power GmbH
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Patent number: 11329182Abstract: A monolithic multiple solar cell includes at least three partial cells, with a semiconductor mirror placed between two partial cells. The aim of the invention is to improve the radiation stability of said solar cell. For this purpose, the semiconductor mirror has a high degree of reflection in at least one part of a spectral absorption area of the partial cell which is arranged above the semiconductor mirror and a high degree of transmission within the spectral absorption range of the partial cell arranged below the semiconductor mirror.Type: GrantFiled: March 23, 2021Date of Patent: May 10, 2022Assignee: AZUR SPACE Solar Power GmbHInventors: Matthias Meusel, Gerhard Strobl, Frank Dimroth, Andreas Bett
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Publication number: 20220140088Abstract: A stacked, high-blocking III-V semiconductor power diode having a first metallic terminal contact layer, formed at least in regions, and a highly doped semiconductor contact region of a first conductivity type and a first lattice constant. A drift layer of a second conductivity type and having a first lattice constant is furthermore provided. A semiconductor contact layer of a second conductivity, which includes an upper side and an underside, and a second metallic terminal contact layer are formed, and the second metallic terminal contact layer being integrally connected to the underside of the semiconductor contact layer, and the semiconductor contact layer having a second lattice constant at least on the underside, and the second lattice constant being the lattice constant of InP, and the drift layer and the highly doped semiconductor contact region each comprising an InGaAs compound or being made up of InGaAs.Type: ApplicationFiled: January 19, 2022Publication date: May 5, 2022Applicants: AZUR SPACE Solar Power GmbH, 3-5 Power Electronics GmbHInventors: Daniel FUHRMANN, Gregor KELLER, Clemens WAECHTER, Volker DUDEK
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Patent number: 11316058Abstract: A stacked multi-junction solar cell with a metallization comprising a multilayer system, wherein the multi-junction solar cell has a germanium substrate forming a bottom side of the multi-junction solar cell, a germanium subcell, and at least two III-V subcells, the multilayer system of the metallization has a first layer, comprising gold and germanium, a second layer comprising titanium, a third layer, comprising palladium or nickel or platinum, with a layer thickness, and at least one metallic fourth layer, and the multilayer system of the metallization covers at least one first and second surface section and is integrally connected to the first and second surface section, wherein the first surface section is formed by the dielectric insulation layer and the second surface section is formed by the germanium substrate or by a III-V layer.Type: GrantFiled: August 31, 2020Date of Patent: April 26, 2022Assignee: AZUR SPACE Solar Power GmbHInventors: Wolfgang Koestler, Benjamin Hagedorn
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Publication number: 20220115501Abstract: A stacked high barrier III-V power semiconductor diode having an at least regionally formed first metallic terminal contact layer and a heavily doped semiconductor contact region of a first conductivity type with a first lattice constant, a drift layer of a second conductivity type, a heavily doped metamorphic buffer layer sequence of the second conductivity type is formed. The metamorphic buffer layer sequence has an upper side with the first lattice constant and a lower side with a second lattice constant. The first lattice constant is greater than the second lattice constant. The upper side of the metamorphic buffer layer sequence is arranged in the direction of the drift layer. A second metallic terminal contact layer is arranged below the lower side of the metamorphic buffer layer sequence. The second metallic terminal contact layer is integrally bonded with a semiconductor contact layer.Type: ApplicationFiled: December 22, 2021Publication date: April 14, 2022Applicant: AZUR SPACE Solar Power GmbHInventors: Daniel FUHRMANN, Gregor KELLER, Clemens WAECHTER
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Patent number: 11296248Abstract: A solar cell stack, having a first semiconductor solar cell having a p-n junction made of a first material with a first lattice constant, and a second semiconductor solar cell having a p-n junction made of a second material with a second lattice constant, and the first lattice constant being at least 0.008 ? smaller than the second lattice constant, and a metamorphic buffer, the metamorphic buffer being formed between the first semiconductor solar cell and the second semiconductor solar cell, and the metamorphic buffer including a series of three layers, and the lattice constant increasing in a series in the direction of the semiconductor solar cell, and the lattice constants of the layers of the metamorphic buffer being bigger than the first lattice constant, two layers of the buffer having a doping, and the difference in the dopant concentration between the two layers being greater than 4E17 cm?3.Type: GrantFiled: November 10, 2015Date of Patent: April 5, 2022Assignee: AZUR SPACE Solar Power GmbHInventors: Daniel Fuhrmann, Wolfgang Guter
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Patent number: 11280025Abstract: A vapor phase epitaxy method including: providing a III-V substrate of a first conductivity type, introducing the III-V substrate into a reaction chamber of a vapor phase epitaxy system at a loading temperature, heating the III-V substrate from the loading temperature to an epitaxy temperature while introducing an initial gas flow, depositing a III-V layer with a dopant concentration of a dopant of the first conductivity type on a surface of the III-V substrate from the vapor phase from an epitaxial gas flow, fed into the reaction chamber and comprising the carrier gas, the first precursor, and at least one second precursor for an element of main group III, wherein during the heating from the loading temperature to the epitaxy temperature, a third precursor for a dopant of the first conductivity type is added to the initial gas flow.Type: GrantFiled: December 21, 2020Date of Patent: March 22, 2022Assignee: AZUR SPACE Solar Power GmbHInventors: Clemens Waechter, Gregor Keller
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Publication number: 20220077343Abstract: A stacked monolithic multi-junction solar cell having at least four subcells, wherein the band gap increases starting from the first subcell in the direction of the fourth subcell, each subcell has an n-doped emitter and a p-doped base, the emitter and the base of the first subcell each are formed of germanium, all following subcells each have at least one element of main group III and V of the periodic table, all subcells following the first subcell are formed lattice-matched to one another, a semiconductor mirror having a plurality of doped semiconductor layers with alternately different refractive indices is placed between the first and second subcell, the semiconductor layers of the semiconductor mirror are each formed n-doped and each have a dopant concentration of at most 5ยท1018 cm?3, the semiconductor mirror is placed between the first subcell and the first tunnel diode.Type: ApplicationFiled: September 7, 2021Publication date: March 10, 2022Applicant: AZUR SPACE Solar Power GmbHInventors: Alexander BERG, Matthias MEUSEL
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Publication number: 20220077342Abstract: A stacked monolithic multi-junction solar cell having at least four subcells, wherein the band gap increases starting from the first subcell in the direction of the fourth subcell, each subcell has an n-doped emitter and a p-doped base, the emitter and the base of the first subcell each have germanium or consist of germanium, all following subcells each have at least one element of main group III and V of the periodic table, a tunnel diode with a p-n junction is placed between each two subcells, all subcells following the first subcell are formed lattice-matched to one another, a semiconductor mirror having a plurality of doped semiconductor layers with alternately different refractive indices is placed between the first and second subcell, and the semiconductor mirror is placed between the first subcell and the first tunnel diode.Type: ApplicationFiled: September 7, 2021Publication date: March 10, 2022Applicant: AZUR SPACE Solar Power GmbHInventors: Matthias MEUSEL, Alexander BERG, Wolfgang GUTER
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Patent number: 11257909Abstract: A stacked, high-blocking III-V semiconductor power diode having a first metallic terminal contact layer, formed at least in regions, and a highly doped semiconductor contact region of a first conductivity type and a first lattice constant. A drift layer of a second conductivity type and having a first lattice constant is furthermore provided. A semiconductor contact layer of a second conductivity, which includes an upper side and an underside, and a second metallic terminal contact layer are formed, and the second metallic terminal contact layer being integrally connected to the underside of the semiconductor contact layer, and the semiconductor contact layer having a second lattice constant at least on the underside, and the second lattice constant being the lattice constant of InP, and the drift layer and the highly doped semiconductor contact region each comprising an InGaAs compound or being made up of InGaAs.Type: GrantFiled: April 30, 2020Date of Patent: February 22, 2022Assignees: AZUR SPACE Solar Power GmbH, 3-5 Power Electronics GmbHInventors: Daniel Fuhrmann, Gregor Keller, Clemens Waechter, Volker Dudek
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Patent number: 11245012Abstract: A stacked high barrier III-V power semiconductor diode having an at least regionally formed first metallic terminal contact layer and a heavily doped semiconductor contact region of a first conductivity type with a first lattice constant, a drift layer of a second conductivity type, a heavily doped metamorphic buffer layer sequence of the second conductivity type is formed. The metamorphic buffer layer sequence has an upper side with the first lattice constant and a lower side with a second lattice constant. The first lattice constant is greater than the second lattice constant. The upper side of the metamorphic buffer layer sequence is arranged in the direction of the drift layer. A second metallic terminal contact layer is arranged below the lower side of the metamorphic buffer layer sequence. The second metallic terminal contact layer is integrally bonded with a semiconductor contact layer.Type: GrantFiled: April 30, 2020Date of Patent: February 8, 2022Assignee: AZUR SPACE Solar Power GmbHInventors: Daniel Fuhrmann, Gregor Keller, Clemens Waechter
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Patent number: 11227969Abstract: A marking method for applying a unique identification to each individual solar cell stack of a semiconductor wafer, at least comprising the steps: Providing a semiconductor wafer having an upper side and an underside, which comprises a Ge substrate forming the underside; and generating an identification with a unique topography by means of laser ablation, using a first laser, on a surface area of the underside of each solar cell stack of the semiconductor wafer, the surface area being formed in each case by the Ge substrate or by an insulating layer covering the Ge substrate.Type: GrantFiled: August 31, 2020Date of Patent: January 18, 2022Assignee: AZUR SPACE Solar Power GmbHInventors: Wolfgang Koestler, Steffen Sommer, Alexander Frey
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Publication number: 20220013679Abstract: A monolithic metamorphic multi-junction solar cell comprising a first III-V subcell and a second III-V subcell and a third III-V subcell and a fourth Ge subcell, wherein the subcells are stacked on top of each other in the indicated order, and the first subcell forms the topmost subcell, and a metamorphic buffer is formed between the third subcell and the fourth subcell and all subcells each have an n-doped emitter layer and a p-doped base layer, and the emitter layer of the second subcell is greater than the base layer.Type: ApplicationFiled: July 12, 2021Publication date: January 13, 2022Applicant: AZUR SPACE Solar Power GmbHInventors: Matthias MEUSEL, Daniel FUHRMANN
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Publication number: 20220013677Abstract: A monolithic multi-junction solar cell comprising a first III-V subcell and a second III-V subcell and a third III-V subcell and a fourth Ge subcell, wherein the subcells are stacked on top of one another in the specified order, and the first subcell forms the top subcell and a metamorphic buffer is formed between the third subcell and the fourth subcell and all subcells each have an n-doped emitter layer and a p-doped base layer and the emitter doping in the second subcell is lower than the base doping.Type: ApplicationFiled: July 12, 2021Publication date: January 13, 2022Applicant: AZUR SPACE Solar Power GmbHInventors: Matthias MEUSEL, Alexander BERG, Philipp SCHROTH
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Publication number: 20220013676Abstract: A stacked monolithic multijunction solar cell, which includes a first subcell having a p-n junction with an emitter layer and a base layer, the thickness of the emitter layer being less than the thickness of the base layer at least by a factor of ten, and the first subcell comprising a substrate having a semiconductor material from the groups III and V or a substrate from the group IV, and which further includes a second subcell arranged on the first subcell and a third subcell arranged on the second subcell, the two subcells each including an emitter layer and a base layer, and a tunnel diode and a back side field layer each being formed between the subcells, the thickness of the emitter layer being greater than the thickness of the base layer in each case between the second subcell and in the third subcell.Type: ApplicationFiled: July 12, 2021Publication date: January 13, 2022Applicant: AZUR SPACE Solar Power GmbHInventors: Daniel FUHRMANN, Rosalinda VAN LEEST, Gregor KELLER, Matthias MEUSEL
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Publication number: 20220013678Abstract: A monolithic metamorphic multi-junction solar cell comprising a first III-V subcell and a second III-V subcell and a third III-V subcell and a fourth Ge subcell, wherein the subcells are stacked on top of each other in the indicated order, and the first subcell forms the topmost subcell, and a metamorphic buffer is formed between the third subcell and the fourth subcell and all subcells each have an n-doped emitter layer and a p-doped base layer, and the emitter layer of the second subcell is greater than the base layer.Type: ApplicationFiled: July 12, 2021Publication date: January 13, 2022Applicant: AZUR SPACE Solar Power GmbHInventors: Matthias MEUSEL, Alexander BERG, Philipp SCHROTH, Susanne SCHREIER
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Publication number: 20220005942Abstract: A vertical high-blocking III-V bipolar transistor, which includes an emitter, a base and a collector. The emitter has a highly doped emitter semiconductor contact region of a first conductivity type and a first lattice constant. The base has a low-doped base semiconductor region of a second conductivity type and the first lattice constant. The collector has a layered low-doped collector semiconductor region of the first conductivity type with a layer thickness greater than 10 ?m and the first lattice constant. The collector has a layered highly doped collector semiconductor contact region of the first conductivity type. A first metallic connecting contact layer is formed in regions being integrally connected to the emitter. A second metallic connecting contact layer is formed in regions being integrally connected to the base. A third metallic connecting contact region is formed at least in regions being arranged beneath the collector.Type: ApplicationFiled: July 6, 2021Publication date: January 6, 2022Applicant: AZUR SPACE Solar Power GmbHInventors: Gregor KELLER, Clemens WAECHTER, Daniel FUHRMANN
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Patent number: 11211516Abstract: A stack-like III-V semiconductor product comprising a substrate and a sacrificial layer region arranged on an upper side of the substrate and a semiconductor layer arranged on an upper side of the sacrificial layer region. The substrate, the sacrificial layer region and the semiconductor layer region each comprise at least one chemical element from the main groups III and a chemical element from the main group V. The sacrificial layer region differs from the substrate and from the semiconductor layer in at least one element. An etching rate of the sacrificial layer region differs from an etching rate of the substrate and from an etching rate of the semiconductor layer region at least by a factor of ten. The sacrificial layer region is adapted in respect of its lattice to the substrate and to the semiconductor layer region.Type: GrantFiled: September 28, 2020Date of Patent: December 28, 2021Assignee: AZUR SPACE Solar Power GmbHInventor: Gerhard Strobl
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Patent number: 11164983Abstract: A stacked multi-junction solar cell with a first subcell having a top and a bottom, and with a second subcell. The first subcell is implemented as the topmost subcell so that incident light first strikes the top of the first subcell and after that strikes the second subcell through the bottom. A first tunnel diode is arranged between the bottom of the first subcell and the second subcell. A window layer is arranged on the top of the first subcell, and the band gap of the window layer is larger than the band gap of the first subcell. A cover layer is arranged below metal fingers and above the window layer, and an additional layer is arranged below the cover layer and above the window layer. A thickness of the additional layer is less than the thickness of the window layer.Type: GrantFiled: January 28, 2020Date of Patent: November 2, 2021Assignee: AZUR SPACE Solar Power GmbHInventors: Matthias Meusel, Rosalinda Van Leest, Alexander Berg, Lilli Horst
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Publication number: 20210301423Abstract: A Metalorganic chemical vapor phase epitaxy or vapor phase deposition apparatus, having a first gas source system, a reactor, an exhaust gas system, and a control unit, wherein the first gas source system has a carrier gas source, a bubbler with an organometallic starting compound, and a first supply section leading to the reactor either directly or through a first control valve, the carrier gas source is connected to an inlet of the bubbler through a first mass flow controller by a second supply section, an outlet of the bubbler is connected to the first supply section, and the carrier gas source is connected to the first supply section through a second mass flow controller by a third supply section, the first supply section is connected to an inlet of the reactor through a third mass flow controller.Type: ApplicationFiled: March 24, 2021Publication date: September 30, 2021Applicant: AZUR SPACE Solar Power GmbHInventors: Clemens WAECHTER, Jan STRATE
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Publication number: 20210296509Abstract: A stacked high-blocking III-V semiconductor power diode and manufacturing method, wherein the III-V semiconductor power diode comprises a first highly doped semiconductor contact area, a low-doped semiconductor drift region disposed beneath the first semiconductor contact area, a highly doped second semiconductor contact area disposed beneath the semiconductor drift region, and two terminal contact layers, at least the first semiconductor contact area forms a core stack, the core stack is surrounded by a dielectric frame region along the side face, the upper surface or lower surface of the core stack and the dielectric frame region terminate with each other or form a step with respect to each other, and semiconductor areas of the III-V semiconductor power diode arranged beneath the first semiconductor contact area are each either surrounded by the core stack or form a carrier portion.Type: ApplicationFiled: March 22, 2021Publication date: September 23, 2021Applicant: AZUR SPACE Solar Power GmbHInventors: Thorsten WIERZKOWSKI, Daniel FUHRMANN