Abstract: A method of manufacturing a redistribution circuit structure is provided. First, a substrate is provided. The substrate has a plurality of pads and a passivation layer. The passivation layer has a plurality of first openings exposing a portion of each of the pads, respectively. A first patterned photoresist layer is formed on the passivation layer. The first patterned photoresist layer has a plurality of second openings exposing a portion of each of the pads. A plurality of first bumps is formed in the second openings, respectively. An under ball metal (UBM) material layer is formed over the substrate to cover the first patterned photoresist layer and the first bumps. A plurality of conductive lines is formed on the UBM material layer. The UBM material layer is patterned to form a plurality of UBM layers using the conductive lines as a mask.

Abstract: A packaging method is disclosed that comprises attaching a plurality of dice, each having a plurality of bonding pads disposed on an active surface, to an adhesive layer on a substrate. A polymer material is formed over at least a portion of both the substrate and the plurality of dice and a molding apparatus is used on the substrate to force the polymer material to substantially fill around the plurality of dice. The molding apparatus is removed to expose a surface of the polymer material and a plurality of cutting streets is formed on an exposed surface of the polymer material.

Abstract: A wafer treating method for making adhesive chips is provided. A liquid adhesive with two-stage property is coated on a surface of a wafer. Then, the wafer is pre-cured to make the liquid adhesive transform an adhesive film having B-stage property which has a glass transition temperature between ?40 and 175 degree C., for example. After positioning the wafer, the wafer is singulated to form a plurality of chips with adhesive for chip-to-chip stacking, chip-to-substrate or chip-to-lead frame attaching.

Abstract: A method of forming a plurality of elastic probes in a row is disclosed. Firstly, a substrate is provided, then, a shaping layer is formed on the substrate so as to offer two flat surfaces in parallel. A photoresist layer is formed on the substrate and on the shaping layer. Then, the photoresist layer is patterned to form a plurality of slots crossing an interface between the two flat surfaces where a plurality of elastic probes are formed in the slots. In one embodiment, the interface is an edge slope of the shaping layer so that each of the elastic probes has at least an elastic bending portion. During chip probing, the shifting direction of the elastic probes due to overdrives is perpendicular to the arranging direction of the bonding pads so that the elastic probes are suitable for probing chips with high-density and fine-pitch bonding pads.

Abstract: A chip package includes a patterned conductive layer, a first solder resist layer, a second solder resist layer, a chip, bonding wires and a molding compound. The patterned conductive layer has a first surface and a second surface opposite to each other. The first solder resist layer is disposed on the first surface. The second solder resist layer is disposed on the second surface, wherein a part of the second surface is exposed by the second solder resist layer. The chip is disposed on the first solder resist layer, wherein the first solder resist layer is disposed between the patterned conductive layer and the chip. The bonding wires are electrically connected to the chip and the patterned conductive layer exposed by the second solder resist layer. The molding compound encapsulates the pattern conductive layer, the first solder resist layer, the second solder resist layer, the chip and the bonding wires.

Abstract: A Quad Flat Non-leaded (QFN) chip package including a patterned conductive layer, a first solder resist layer, a chip, a plurality of bonding wires and a molding compound is provided. The patterned conductive layer has a first surface and a second surface opposite to each other. The first solder resist layer is disposed on the first surface, wherein a part of the first surface is exposed by the first solder resist layer. The chip is disposed on the first solder resist layer, wherein the first solder resist layer is between the patterned conductive layer and the chip. The bonding wires are electrically connected to the chip and the patterned conductive layer exposed by the first solder resist layer. The molding compound encapsulates the pattern conductive layer, the first solder resist layer, the chip and the bonding wires.

Abstract: A chip package including a carrier having an opening, a first chip, bumps, a second chip, bonding wires, a first adhesive layer and a molding compound is provided. The first chip and the second chip are disposed at two opposite side of the carrier. The bumps are disposed between the carrier and a first active surface of the first chip to electrically connect with the first chip and the carrier. The bonding wires pass through the opening of the carrier and are electrically connected with the carrier and the second chip. The first adhesive layer adhered between the first active surface of the first chip and the carrier includes a first B-staged adhesive layer adhered on the first active surface of the first chip and a second B-staged adhesive layer adhered between the first B-staged adhesive layer and the carrier.

Abstract: A chip package including a circuit substrate having an opening, a first chip, first bonding wires, a component, a first adhesive layer and a molding compound is provided. The first chip has a first active surface and a first rear surface opposite to the first active surface, the first chip is flipped on and electrically connected with the circuit substrate. The first bonding wires are electrically connected with the circuit substrate and the first chip, and each first bonding wire passes through the opening. The component is disposed over the first rear surface. The first adhesive layer adhered between the first rear surface and the component includes a first B-staged adhesive layer adhered on the first rear surface and the component and a second B-staged adhesive layer adhered between the first B-staged adhesive layer and the component. The molding compound is disposed on the circuit substrate.

Abstract: A chip package including a circuit substrate, a first chip, first bonding wires, a component, a first adhesive layer and a molding compound is provided. The first chip has a first active surface, a first rear surface and first bonding pads, the first rear surface is adhered on the circuit substrate and the first chip is electrically connected with the circuit substrate. The first bonding wires are electrically connected with the circuit substrate and the first bonding pads of the first chip. The component is disposed over the first active surface of the first chip. The first adhesive layer adhered between the first active surface and the component without covering the first bonding pads and includes a first B-staged adhesive layer adhered on a portion of the first active surface of the first chip and a second B-staged adhesive layer adhered between the first B-staged adhesive layer and the component.

Abstract: A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.

Abstract: A chip package structure including a chip, a lead frame, first bonding wires and second bonding wires is provided. The chip has an active surface, first bonding pads and second bonding pads, wherein the first bonding pads and the second bonding pads are disposed on the active surface. The chip is fixed below the lead frame, and the lead frame includes inner leads and bus bars. The inner leads and the bus bars are disposed above the active surface of the chip, and the bus bars are located between the inner leads and the corresponding first bonding pads. The first bonding wires respectively connect the first bonding pads and the bus bars. The second bonding wires respectively connect the bus bars and a part of the inner leads. The third bonding wires respectively connect the second bonding pads and the other of the inner leads.

Abstract: A chip package structure includes a substrate, a chip, a first B-stage adhesive, bonding wires, a heat sink and a molding compound. The substrate comprises a first surface, a second surface and a through hole. The chip is arranged on the first surface of the substrate and electrically connected thereto while the through hole of the substrate exposes a portion of the chip. The first B-stage adhesive is arranged between the chip and the first surface of the substrate, and the chip is attached to the substrate through the first B-stage adhesive. The bonding wires are connected between the chip exposed by the through hole and second surface of the substrate. The heat sink is arranged on the first surface of the substrate, covering the chip. The molding compound is arranged on the second surface of the substrate, covering a portion of the substrate and bonding wires.

Abstract: A fabricating process of chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provide, wherein a plurality of bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate or on the second substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the first B-staged adhesive layer and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.

Abstract: A fabricating process of a chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provide, wherein a plurality of bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the second substrate and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.

Abstract: The present invention provides a flexible substrate for a package of a die which has an active surface and a plurality of first bond pads arranged in a form of a row and formed on the active surface. The flexible substrate includes a flexible insulating film and a plurality of first leads formed on the flexible insulating film. Each of the first leads corresponds to one of the first bond pads and has a respective first body portion, a respective first bond portion and a respective first extension portion. For each of the first leads, the width of the first bond portion is larger than those of the first body portion and the first extension portion.

Abstract: A chip package structure including a first substrate, a second substrate, a plurality of bumps, a first B-staged adhesive layer and a second B-staged adhesive layer is provided. The first substrate has a plurality of first bonding pads. The second substrate has a plurality of second bonding pads, and the second substrate is disposed above the first substrate. The bumps are disposed between the first substrate and the second substrate, wherein each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps. The first B-staged adhesive layer is adhered on the first substrate. The second B-staged adhesive layer is adhered between the first B-staged adhesive layer and the second substrate, wherein the first B-staged adhesive layer and the second B-staged adhesive layer encapsulate the bumps.

Abstract: A chip package without a core, including a patterned circuit layer, a chip, a solder mask, a molding compound and multiple outer terminals, is provided. The patterned circuit layer has a first surface and a second surface opposite to each other. The chip disposed on the first surface is electrically connected to the patterned circuit layer. The solder mask disposed on the second surface has a plurality of first openings by which part of the patterned circuit layer is exposed. The molding compound with a plurality of through holes cover the pattern circuit layer and fix the chip onto the patterned circuit layer. Each outer terminal disposed in the through hole is electrically connected to the patterned circuit layer.

Abstract: A chip package structure mainly including a substrate, a chip and a lead frame is provided. The chip is disposed on the substrate, and is electrically connected to the chip by flip-chip or wire-bonding technique. The chip is electrically connected to the lead frame through a redistribution layer on the substrate. Therefore, a problem that the bonding wires may collapse due to a longer distance between the chip and the lead frame may be resolved, thus improving the yield rate thereof.

Abstract: A method of fabricating a chip package is provided. A thin metal plate having a first protrusion part, a second protrusion part and a plurality of third protrusion parts are provided. A chip is disposed on the thin metal plate, and a plurality of bonding wires for electrically connecting the chip to the second protrusion part and the second protrusion part to the third protrusion parts is formed. An upper encapsulant and a lower encapsulant are formed on the upper surface and the lower surface of the thin metal plate respectively. The lower encapsulant has a plurality of recesses for exposing a portion of the thin metal plate at locations where the first protrusion part, the second protrusion part and the third protrusion parts are connected to one another. Finally, the thin metal plate is etched by using the lower encapsulant as an etching mask.

Abstract: An assembly device of an image sensor chip is disclosed. A flexible circuit has a die-attached portion, a plurality of bendable portions, and a plurality of bonding portions where the bendable portions extend from the die-attached portion and are connected to the corresponding bonding portions. A plurality of inner leads are formed on the bonding portions. An image sensor chip with bumps is attached to the die-attached portion. The bendable portions are so bent that the bonding portions are located above the image sensor chip. By thermocompression bonding, the inner leads of the flexible circuit are bonded to the bumps on the image sensor chip. In one embodiment, a transparent cover is adhered to the bonding portions and located above a sensing area of the image sensor chip.