Abstract: The invention relates to high-resolution analog-digital converters using so-called folding differential amplifier structures composed of differential circuits (crossed differential pairs) and of loads (cascode transistors). The folding structure according to the invention comprises, in the case where it is desired to produce four curves folded at two periods in the useful range of voltages to be converted, four folding blocks (one per curve). The first comprises 7 differential circuits and eight loads, the end loads not being linked to the output of the block. The other blocks comprise 6 differential circuits and eight loads, the last load of each block not being linked to the output of this block. Gains are achieved in terms of bulk, consumption and operating speed, with respect to existing structures.

Abstract: The invention relates to matrix-array image sensors with MOS-technology active pixels, comprising a matrix-array of pixels arranged in rows and columns. To read the signal from a pixel, the reset potential present on a column conductor is sampled in two capacitors.

Abstract: The invention relates to the fabrication of electronic circuits on a thinned semiconductor substrate. To produce a connection pad on the back side of the thinned substrate, the procedure is as follows: an integrated circuit is produced on an unthinned substrate, in which a portion of a polycrystalline silicon layer (18) dedicated for the connection of the pad is provided. The circuit is transferred onto a transfer substrate (30) and then its back side is thinned. A via is opened in the thinned semiconductor layer (12) in order to gain access to the polycrystalline silicon; aluminum (80) is deposited and this layer is etched so as to define a pad which is in contact with the internal interconnects of the integrated circuit by way of the polycrystalline silicon.

Abstract: The invention relates to image sensors and more particularly those which are intended to capture images at low luminance levels. An active-pixel image sensor is provided, each pixel comprising, on the surface of a semiconductor active layer, a photodiode region adjacent a transfer gate itself adjacent a charge storage region, the transfer gate permitting, when it receives a transfer pulse, the transfer of charge from the photodiode region to the storage region. The photodiode region is adjacent an accelerating gate isolated from the semiconductor active layer. Switching means are provided so as to apply to the accelerating gate, during an integration phase preceding the transfer pulse, a series of high-potential/low-potential alternations inducing an electric field alternately in one direction and in the other direction between the photodiode region and the active layer region located beneath the accelerating gate.

Abstract: The invention relates notably to large-sized image sensors or image sensors with a large number of rows. Each column of pixels is organized in P superposed blocks. A row decoder organized as P identical decoders selects one row out of M in each of the P blocks. Each block is linked to one respective column conductor out of P column conductors. P read circuits CL1 to CL4 are placed at the foot of each column of pixels and each is connected to a respective column conductor. The signals from the P rows selected by the decoder can be extracted simultaneously or else they can be selected by a specific decoder which selects one read circuit out of the P read circuits of each column. The matrix can be produced by photolithography, by abutting identical matrix portions, for example P different portions corresponding to P identical regions ZB1 to ZB4.

Abstract: The invention relates to the fabrication of integrated circuits in general, and notably the circuits of image sensors intended to form the electronic core of photographic apparatus or cameras. The chip is first aligned with respect to the package and then the package is aligned with respect to the optical system. The alignment of the chip with respect to the package is done optically. The alignment of the package with respect to the system is done mechanically with respect to the edges of the package. According to the invention, provision is made for optical marks to be provided on the package, these marks each having an edge aligned with a lateral edge of the package, so as to minimize the positioning errors which would be due to inaccurate positioning of the chip with respect to the edges of the package.

Abstract: The invention relates to image sensors produced on a thinned silicon substrate. To limit the optical crosstalk between adjacent filters and, notably filters of different colors, the invention proposes positioning, between the adjacent filters of different colors (FR, FB, FV), a wall (20) of a material tending to reflect the light so that the light arriving obliquely on a determined filter corresponding to a first pixel does not tend to pass toward an adjacent filter or toward a photosensitive zone corresponding to an adjacent pixel but is returned by the wall to the first filter or the photosensitive zone corresponding to the first pixel. The wall is preferably made of a material with a high reflection coefficient such as aluminium and it is sunk depthwise into the thinned semiconductor layer (16), preferably in p+ diffusions formed in the layer if it is of p-type.

Abstract: The invention relates to an electronic circuit making it possible to extract a clock signal from an incident binary data sequence arriving at a constant rate. The electronic circuit comprises an oscillator (VCO) with voltage-controlled frequency providing a sinusoidal signal, a circuit (R, Cp, RD, I1, I2) for extracting the transition edges of the binary sequence producing a brief pulse at each transition, a sampler (MLT) for tapping off the level of the sinusoidal voltage at the instant of the brief pulse, and an integrator (AOP, R1, C1) for integrating this level in tandem with the successive pulses, the output of the integrator being applied as control voltage to the oscillator with controlled frequency, the output of the oscillator being the desired clock frequency with a slaved phase passing through zero substantially in the middle of the interval between two binary data transitions.

Abstract: The invention relates to image sensors with active pixels. To obtain a wide dynamic operating range, the pixels are read by performing a double charge integration, during periods of different values (Ti1, Ti2). The result of the first integration (period Ti1) is sampled (command SHS1) in a sampling capacitor, and the result of the second integration (period Ti2) is conditionally sampled (command SHS2) in the same capacitor. This second sampling depends on the observation of the potential of the column conductor after the integration of charges corresponding to the longer period; this potential is compared to a threshold. If the comparison indicates a risk of saturation, the information collected during the shorter period is collected and retained in the sampling capacitor in order for it to be multiplied by a coefficient representing the ratio between the longer period and the shorter period.

Abstract: The invention relates to circuits for managing differential voltages in series. To individually control the differential voltages of voltage sources in series, there is provided an integrated control circuit for a set of N sources in series. This circuit comprises N discharge control and measurement cells which are each produced in a separate well, insulated from the substrate and from the other wells. The cells are linked to the circuits formed in the substrate by level translation circuits having a part inside the well and a part outside the well. These circuits use transistors withstanding voltages of several tens of volts. The integrated circuits may be cascaded on an SPI bus if one wishes to control a group of k.N sources with k>1.

Abstract: The present application relates to the fabrication of an electronic component. The component comprises two, superposed integrated circuits: one of which is formed on the front side of a thinned first substrate, and the other of which is produced on the front side of a second substrate, with an insulating planarization layer interposed between the front sides of the two substrates. The silicon of the backside of the thinned substrate is opened locally above a first conducting area located in the thinned substrate and above a second conducting area located in the second substrate. A conducting layer portion, deposited on both areas, electrically connects them so as to provide the interconnection between the two circuits. The external connection pads may also be formed in this conducting layer.

Abstract: The invention relates to the fabrication of thinned substrate image sensors, and notably color image sensors. After the fabrication steps carried out from the front face of a silicon substrate the front face is transferred onto a substrate. The silicon is thinned, and the connection terminals are produced by the rear face. A multiplicity of localized contact holes are opened through the thinning silicon, in the location of a connection terminal. The holes exposing a first conductive layer (24) are formed during the front face steps. Aluminum (42) is deposited on the rear face, in contact with the silicon, with the aluminum penetrating into the openings and coming into contact with the first layer. The aluminum is etched to delimit the connection terminal. Finally, a peripheral trench is opened through the entire thickness of the silicon layer, and this trench completely surrounds the connection terminal.

Abstract: The invention relates to fast, high resolution, analog digital converters, and more particularly those which possess at least one conversion stage of “flash” type. The converter according to the invention uses N differential amplifiers with four inputs. The amplifier of rank j receives the input voltage to be converted Vep?Ven on two first inputs, and a reference potential difference on two other inputs. The reference potential difference is obtained between two taps of networks of resistors that are identical operating in parallel and supplied between a high voltage source and a low current source; the taps for an amplifier are respectively a tap Pj of rank j of a first network and a tap P?N?j+1 of rank N?j+1 of a second network. This reduces the first and second order non-linearity effects due to the fact that the differential amplifiers consume an input current tapped off from the networks of resistors.

Abstract: The invention relates to an intra-oral dental radiology sensor. The sensor comprises an electronic image acquisition module and a molded casing made of a hard plastic which is locally provided with overmoldings made of a softer plastic having the consistency of smooth rubber, covering the hard plastic in areas located on the outside of the casing and corresponding to projecting angular portions of the hard plastic, and also in areas located inside the casing at places where the electronic module may bear. The soft plastic is preferably a copolymer of the SEBS (styrene/ethylene-butylene/styrene) type whereas the hard plastic is preferably a polyamide. The patient's comfort is improved and the module is better protected against shocks without increasing its size.

Abstract: The invention relates to sample-and hold modules, and notably those which are intended to be placed upstream of an analog-digital converter. The sample-and-hold module conventionally comprises a differential pair of transistors, a follower transistor and a storage capacitor. The follower transistor is turned on during a sampling phase by the application of an emitter current by means of a first current switch and can be disabled during a hold phase by the application of a disabling voltage to its base. The sample-and-hold module operates according to the invention with a hold phase beginning at the same time as the end of a sampling phase and terminating before the start of a new sampling phase. Switching spikes are thus avoided at the transition between the end of a hold phase and the start of a new sampling phase.

Abstract: The invention relates to image sensors using a chip with cut corners. The sensor comprises a chip with cut corners comprising a matrix (10) of horizontal lines and vertical columns of photosensitive members, the matrix having a generally rectangular shape of horizontal width W and having four bevels, the sensor comprising as many current or voltage read blocks as there are matrix columns, in order to read the image signals detected by the photosensitive members, characterized in that the current or voltage read blocks are placed in a row (30, 30?) along a horizontal edge of the matrix of width W? and are all housed within a vertical strip, the width W1 of which is substantially less than the maximum width W of the matrix. There are two superposed rows of current read blocks with blocks distributed at the same pitch as the pixel columns, or there is a single row with read blocks distributed with a pitch less than that of the pixel columns.

Abstract: The invention relates to intraoral radiological dental image sensors, i.e. sensors placed in the mouth of a patient, an X-ray source being located outside the cheek of the patient in order to emit X-rays in the direction of the sensor. According to the invention, the image sensor is attached to a first end of a short electrical cable (22) of around 5 to 20 cm, a second end of which leaves the patient's mouth when the sensor is in the mouth, the second end carrying a light source (24) comprising light-emitting diodes that can be digitally modulated as a function of information coming from the sensor, the electrical cable being able to transmit an electrical control signal from the sensor to the diode for modulating the latter.

Abstract: The invention relates to high-resolution analog-digital converters using so-called folding differential amplifier structures composed of differential circuits (crossed differential pairs) and of loads (cascode transistors). The folding structure according to the invention comprises, in the case where it is desired to produce four curves folded at two periods in the useful range of voltages to be converted, four folding blocks (one per curve). The first comprises 7 differential circuits and eight loads, the end loads not being linked to the output of the block. The other blocks comprise 6 differential circuits and eight loads, the last load of each block not being linked to the output of this block. Gains are achieved in terms of bulk, consumption and operating speed, with respect to existing structures.

Abstract: The invention relates to electronic components on thinned substrates, for example image sensors. Preferably, connection pads are connected through the thinned substrate to underlying layers and notably to a test pad by way of openings through which the metal of the pad passes. The openings are elongate openings extending along one edge of the pad of rectangular shape and a circular area of at least 50% (and preferably 65 to 75%) of the area of the pad contains no opening for connection with the underlying layers. This circular area is intended for bonding an external connection wire. The connection pads are testable from the back side by test probes and the front side may be tested (before bonding and thinning) by test probes with the same geometric configuration.

Abstract: The invention relates to an integrated circuit comprising a succession of N identical elementary circuits, juxtaposed in the order of their rank j varying from 1 to N, N being at least equal to 50, and all having to receive two reference potentials Vref and V0 supplied by two conductors. The upstream input of the second conductor is situated geographically on the side of the rank 1 of the succession of juxtaposed circuits, and the upstream input of the first conductor is situated geographically on the side of the rank N of the succession of juxtaposed circuits. This reduces the error in the potential difference applied to the elementary circuits all along the succession, an error that originates from the non-zero resistance of the conductors. Application to analog-digital converters or digital-analog converters with high resolution (10 bits or more).