Abstract: A mass-production transfer support system has a mass-production transfer source managing computer for managing information generated in a trial-production process of a semiconductor device and a mass-production transfer destination managing computer for managing a mass-production process of the semiconductor device.

Abstract: A structure of test element group wiring includes, in addition to an electrode on a substrate including one or more layers of insulating films, and real wirings electrically connected to the electrode, includes dummy wirings electrically isolated from the electrode and having a portion of the same shape as the real wiring. The dummy wirings are disposed at a predetermined constant distance adjacent to the real wirings or to each other, so that the wiring rate of the real wiring relaxes the concentration difference of patterns. The distance between the real wirings is sufficient to perform pattern analysis using the OBIRCH method.

Abstract: A semiconductor device having a gate electrode on a silicon substrate via a gate insulating film is formed by laminating the gate insulating film with a silicon oxide film, formed on the silicon substrate, an Hf silicate film is formed on the silicon oxide film, and a nitrogen-containing Hf silicate film formed on the Hf silicate film, and containing Hf in a peak concentration in a range from one atomic % to thirty atomic %, and nitrogen in a peak concentration in a range from ten atomic % to thirty atomic %.

Abstract: A method of fabricating a semiconductor device includes forming a metal wire on a substrate, forming an interlayer insulating film on the metal wire, forming a resist pattern on the interlayer insulating film, selectively etching the interlayer film to form a trench or via-hole in the interlayer insulating film and reaching the metal wire, and ashing, using a reducing gas, to remove the resist pattern.

Abstract: A catalytic CVD equipment comprises: a vacuum chamber; a stage; a first catalyzer; and a second catalyzer. The stage holds a substrate in the vacuum chamber. The first catalyzer is provided in the vacuum chamber and has a bar member arranged substantially in parallel to a major surface of the substrate. The second catalyzer is provided in the vacuum chamber, and has a bar member arranged at a tilted angle to the major surface of the substrate. A thin film is deposited on the substrate held on the stage by introducing a source gas, by heating the first and the second catalyzer, and by decomposing the gas in the vacuum chamber under a low pressure.

Abstract: A semiconductor device comprises a semiconductor substrate and an interlayer interconnection structure provided on the semiconductor substrate. The interlayer interconnection structure includes a porous insulation film and a conductive part of a conductive material containing a metal as a major component. A volume occupation ratio of pores of a diameter greater than 0.6 nanometers is less than 30% in the porous insulation film.

Abstract: An insulating-film composition containing an insulating-film precursor and a pore-generating material is applied onto a surface of a semiconductor substrate, and a first heat treatment is performed to polymerize the insulating-film precursor without vaporizing the pore-generating material, to form a non-porous insulating film. Next, a resist pattern is formed on the non-porous insulating film, and dry etching is performed, using the resist pattern as a mask, to form a trench in the non-porous insulating film. After removing the resist pattern by ashing, the surface of the semiconductor substrate is cleaned. Next, a second heat treatment is performed to remove the pore-generating material from the non-porous insulating film and to form a porous insulating film. Thereafter, a copper layer is deposited in the trench on a barrier-metal film to form copper wiring.

Abstract: In an exposure step, a combination of a first photomask and a second mask is used. The first mask has a real pattern corresponding to the pattern actually formed on the film to be processed, and a dummy pattern added for controlling pattern pitch in the first photomask within a prescribed range; and the second photomask has a pattern isolating a real-pattern-formed region from a dummy-pattern-formed region. In forming the pattern, after forming a film to be processed on a substrate, a first mask is formed on the film to be processed, by lithography, using the first photomask, and a second mask is formed on the film to be processed, by lithography, using the second photomask. Thereafter, the film to be processed is etched and removed using the first and second masks as masks to form the pattern.

Abstract: An exposure method includes forming a resist film on a substrate to be processed, forming a top anti-reflection coating on the resist film, and irradiating the resist film with exposure light through the top anti-reflection coating. Forming the top anti-reflection coating includes adjusting refractive index and thickness of the top anti-reflection coating to increase a ratio of s-polarized light to p-polarized light in the exposure light entering the resist film.

Abstract: A method for fabricating a high density semiconductor integrated circuit device with a multilayer interconnect wiring structure is disclosed. This structure has a low-dielectric constant insulator film including an organic thin-film with its dielectric constant ranging from about 2.0 to about 2.4. To fabricate the multilayer wiring structure, a substrate with an inorganic film for use as an underlayer dielectric film is prepared. Then, apply plasma processing, such as plasma-assisted chemical vapor-phase growth, to a top surface of the inorganic underlayer dielectric film in environment that contains therein organic silane-based chemical compounds, thereby to form on the inorganic film surface a hydrophobic surface layer with a contact angle with water being 50° or higher. Next, form on the plasma-processed hydrophobic surface an organic film including a fluorinated aromatic carbon hydride polymer film.

Abstract: A gate insulating film is formed in a first region and a second region of a substrate, a first metallic film is formed on the gate insulating film in one of the first region or the second region, and a second metallic film is formed on each of the first and second regions. Furthermore, a protective film is formed on the second metallic film, and the protective film and the metallic film are patterned to the pattern of the gate electrode. Next, a first sidewall is formed on the side of a gate electrode. Then, impurities producing first and second conductivity types are implanted into the surface of the substrate in respective regions, using the first sidewalls and the gate electrodes as masks to form a first impurity-diffused region, and impurities producing second and first conductivity types are implanted to form an impurity diffusion preventing layer.

Abstract: In a method for forming a semiconductor device, the major surface of a substrate is separated into a first element region for forming a first field-effect transistor and a second element region for forming a second field-effect transistor. A silicon nitride film is formed in each of the first and second element regions. Thereafter, the silicon nitride film formed in the second element region is removed, and the substrate is subjected to heat treatment in an ambient that contains nitrogen oxide. Thereby, the silicon nitride film in the first element region is oxidized to form an oxynitride film, and a silicon oxynitride film is formed in the second element region. Thereafter, a high-dielectric-constant film is formed on the silicon oxynitride films in each of the first and second element regions.

Abstract: A cleaning apparatus is provided with a processing bath to be filled with a cleaning chemical, an ultrasonic oscillator, and a retainer for holding a substrate to be immersed into a cleaning chemical. The front surface of the substrate is cleaned while ultrasonic waves are radiated from the ultrasonic oscillator onto the back surface of the substrate.

Abstract: A wafer edge exposure apparatus is provided with an optical section for radiating exposure light onto the edge of a semiconductor wafer. The optical section is provided with a focus sensor for sensing a distance from the lower end of the optical section to the edge of the semiconductor wafer. There is provided a position control mechanism for moving the optical section vertically on the basis of a value detected by the focus sensor such that the distance matches a focal distance of the optical section.

Abstract: A mask layer having an opening is formed on a semiconductor substrate. Next, oxygen ions and a first impurity are implanted into the semiconductor substrate using the mask layer as a mask. Then, the mask layer is removed. Next, the oxygen ions are heat treated to react and form an oxide film on the region where the first impurity has been implanted. Then, the oxide film is removed to form a depression in the semiconductor substrate. Next, a gate insulating film and a gate electrode are formed on the depression. Then a second impurity is implanted into the surface of the semiconductor substrate to form a source/drain. An impurity lighter than the oxygen ions and the second impurity is used as the first impurity.

Abstract: A first CVD dielectric layer is deposited on a surface of a semiconductor substrate. Next, low-k layers are deposited in at least two different steps to form one of a via-layer dielectric film and a wiring-layer dielectric film on the first CVD dielectric layer. Immediately after the depositions, thermal treatment is performed. A second CVD dielectric layer is deposited on the low-k layers. A groove is formed in the second CVD dielectric layer and the low-k layers. A metal layer is deposited on that structure, filling the groove. The metal layer is removed from the second CVD dielectric layer by chemical mechanical polishing.

Abstract: A gate electrode in an NMOS region is one of intrinsic silicon and a material having a work function equivalent to that of intrinsic silicon, and a material having a work function smaller than that of intrinsic silicon. A gate electrode in a PMOS region is one of intrinsic silicon and a material having a work function equivalent to that of intrinsic silicon, and a material having a work function larger than that of intrinsic silicon. Further, a source/drain region in the NMOS region includes a silicide layer of a material having a work function smaller than that of intrinsic silicon, and a source/drain region in the PMOS region includes a silicide layer of a material having a work function larger than that of intrinsic silicon.

Abstract: A semiconductor device of the present invention comprises: a silicon substrate; a gate insulating film on the silicon substrate; and a gate electrode on the gate insulating film, wherein the gate insulating film includes: a first insulating film; a second insulating film on the first insulating film; and a metal nitride film on the second insulating film. The metal nitride film may be either AlN or Hf3N4. The metal nitride film may include nitrides of two or more different metals.

Abstract: A method of depositing lithium phosphorus oxynitride on a substrate, the method comprising loading a substrate into a vacuum chamber having a target comprising lithium phosphate, introducing a process gas comprising nitrogen into the chamber and maintaining the gas at a pressure of less than about 15 mTorr; and forming a plasma of the process gas in the chamber to deposit lithium phosphorous oxynitride on the substrate.

Abstract: A first insulating film is formed on a base substrate, then a second insulating film is formed on the first insulating film, the second insulating film having a relative permittivity higher than that of the first insulating film. A gate electrode is formed on the second insulating film. The second insulating film forming includes first to sixth steps, and a cycle consisting of the first to sixth steps is repeated.