Abstract: An improved segmented digital to analog converter is provided, configured with a novel method of compensating current flow in secondary or successive segmented elements. In operation, dual current devices initially load, then subsequently unload a cascade of resistor networks connected to the secondary or successive voltage segmenting elements, preventing the perturbation of precise operation of the primary or preceding elements. In contrast to conventional approaches, the improved converter obviates the need for a buffer or amplifier to isolate the secondary and successive voltage segmenting elements from the primary or preceding elements.

Abstract: A high quality DAC is provided for a lower cost (including the layout size of the circuit on an audio chip) of high end DACs. The DAC includes a first circuit configured to remove even harmonics from a sigma delta circuit, and a second circuit configured to remove odd harmonics.

Abstract: A sigma delta modulation loop circuit and related method is provided for use in a device having a radio frequency receiver. The loop is configured to compensate for noise that is generated by the sigma delta loop and that affects radio signals within the range of a radio frequency band according to the operating frequency of the radio frequency tuner.

Abstract: The disclosure is a solid-state imaging device, including a photosensor for collecting charge created by incident photons, a comparator for comparing a digital voltage value corresponding to the collected charge, to a predetermined value, and generating a comparison output, and a normalizing circuit for normalizing the digital voltage value, in response to the comparison output.

Abstract: A sigma delta circuit is provided having a sigma delta modulator configured to operate according to a first clock signal and a quantizer connected to the sigma delta modulator, where the quantizer is configured to operate according to a second clock signal. In operation, if a small amplitude signal is received by the sigma delta circuit, the circuit is configured to operate at a fixed output frequency. When a large amplitude signal is received, the circuit is configured to adjust to a different frequency to accommodate the larger signal. The second clock signal may be a variable clock signal, where the quantizer operates according to a variable clock signal in order to adjust to different input signals.

Abstract: The invention provides a frequency locked loop and related method that enables the conversion of a signal frequency with improved stability. A frequency locked loop embodying the invention includes an input for receiving an input signal and an output for outputting an output signal having a different frequency than the input. A frequency detector is configured to receive the first factored input from the primary channel and the second factored input from the secondary channel, to calculate the difference between the first factored input and the second factored input and to produce an output based on the difference between the two factored inputs. A voltage controlled oscillator is configured to receive the output from the frequency detector, and to produce an output signal. The voltage controlled oscillator ultimately sets the output frequency based on the output of frequency detector.

Abstract: A one time programmable solid-state device is provided such that the programmable solid-state device includes a programmable memory unit embedded in a die and a driver circuit that programs the programmable memory unit. The one time programmable solid-state device also includes an access circuit that enables access to the programmable memory unit. In an example operation when the one-time programmable solid-state is a solid-state image device, the one-time programmable solid-state device performs the process of identifying an address of a defective pixel in a photosensor having a plurality of pixels arranged in a two-dimensional array in the die and storing the address in the programmable memory unit that is embedded in the die of the solid-state imaging device.

Abstract: An exemplary CMOS image sensor comprises a reset transistor, a photodiode, reset drain voltage circuitry, and reset gate voltage circuitry. A cathode of the photodiode is connected to a source of the reset transistor, and an anode of the photodiode is connected to ground. The reset drain voltage circuitry is connected to a drain of the reset transistor, and the reset gate voltage circuitry is connected to a gate of the reset transistor. During an exemplary hard reset operation, the reset drain voltage circuitry supplies a first drain voltage to the drain of the reset transistor in accordance with a determined level of light for exposure, which is determined dynamically. According to another exemplary reset operation, a hard reset phase is immediately followed by a soft reset phase.

Abstract: An imager cell includes a photoreceptor, a sense node, and a pinned transfer gate. The pinned transfer gate is tied to the same potential of a substrate of the imager cell and is disposed between the photoreceptor and the sense node in order to transfer charge between the photoreceptor and the sense node. The imager further includes a reset transistor disposed to reset the sense node, and an output amplifier coupled to the sense node. Control circuitry supplies a photoreceptor readout clock to the photoreceptor. The readout clock includes an integration period and a transfer period. According to various embodiments of the invention, the imager cell provides improved noise performance, selective charge capacities, and improved blue light response beyond that of conventional imager cells.

Abstract: A circuit and related method for digital volume control are provided, where the circuit includes a digital filter configured to process samples of an input stream in a manner that processes a previous input sample during a time interval before a subsequent input sample, and outputs a series of exponentially decaying waveforms. The result is an exponential response to a volume change made by a user, where the change feels more pleasant and natural than a conventional linear response.

Abstract: A sensor may be formed with a transistor comprising a gate that has both n-type and p-type regions to increase the gate work function. In combination with moving the p-type well such that the p-type well only partially dopes the channel of the transistor, the increased gate work function further increases the reset voltage level required to create the reset channel without having to use high doping levels in the critical regions of the sensor structure including the photo-detector and the reset transistor. The source of the reset transistor is partially beneath the n-type region of gate, while the transistor's drain is partially beneath the p-type region of the gate. The channel has a p-type well portion and a substrate portion. This construction of the sensor may eliminate the reset noise associated with the uncertainty of whether the charge left in the transistor's channel will flow back towards the photo-detector after the transistor has been turned off.

Abstract: A device and method are provided for implementing digital baseband separation of composite video signals with reduced memory requirements. The method and device require that only the composite signal be stored in a large delay element. Multiple quadrature demodulators are employed to generate multiple delayed complex baseband signals. Therefore, no large complex baseband delay element is required.

Abstract: A device is provided having at least two capacitive elements configured to retain a charge, and an interconnection of active devices between the capacitive elements. The active devices are configured to operate upon a transient charge flow as a current when in operation. The charge flow is partitioned into at least two capacitors according to the input voltage difference acting as a controlling parameter.

Abstract: A differential input flash analog-to-digital converter in which an array of comparators is connected to compare reference signals within a parabolic distribution of such signals generated by the application of a differential input signal across an impedance network. Preferably, the comparator array comprises at least two pluralities of comparators, the first plurality of comparators comparing pairs of reference nodes separated by a first step size, and the second plurality of comparators comparing pairs of reference nodes separated by a second step size. Even more preferably, the comparator array further comprises a third plurality of comparators comparing pairs of reference nodes separated by a third step size, but only where necessary to maximize the available comparison range of the converter. The flash converter according to the invention provides increased gain from input without accumulation of comparator input currents and without sacrificing the number of actual comparisons of reference signals.

Abstract: An imager includes an array of imager cells coupled to a multi-mode controller. The multi-mode controller includes circuitry that implements several modes of operation, including a high-light mode, a low-light mode, and a Snap mode. The high-light mode provides charge accumulation in a photoreceptor potential well, a readout potential well, and a sense node potential well. The low-light mode provides charge accumulation in the photoreceptor potential well constrained by an integration potential well. The Snap mode of operation simultaneously transfers accumulated charge for a set of the imager cells to their sense nodes. In addition, the multi-mode controller may select one of a plurality of V+ integration voltages for setting up a selected charge capacity in one of the imager cells. Thus, the V+ integration voltage may be increased to provide charge capacity to address increased light levels.

Abstract: A circuit and related method for digital volume control are provided, where the circuit includes a digital filter configured to process samples of an input stream in a manner that processes a previous input sample during a time interval before a subsequent input sample, and outputs a series of exponentially decaying waveforms. The result is an exponential response to a volume change made by a user, where the change feels more pleasant and natural than a conventional linear response.

Abstract: The invention provides a frequency locked loop and related method that enables the conversion of a signal frequency with improved stability. A frequency locked loop embodying the invention includes an input for receiving an input signal and an output for outputting an output signal having a different frequency than the input. A frequency detector is configured to receive the first factored input from the primary channel and the second factored input from the secondary channel, to calculate the difference between the first factored input and the second factored input and to produce an output based on the difference between the two factored inputs. A voltage controlled oscillator is configured to receive the output from the frequency detector, and to produce an output signal. The voltage controlled oscillator ultimately sets the output frequency based on the output of frequency detector.

Abstract: An electronic device is provided such as an amplifier, for example, having improved gain and transconductance and low output impedance. The device includes a primary amplifier configured to carry an operating load. The primary amplifier includes an input for receiving an input signal, and an output for outputting an output signal, and operates having a variable output, as it carries an operational load. The device further includes a secondary amplifier configured to operate at a fixed operating condition, not burdened by carrying an operational load, and includes a secondary input configured to receive the input signal, wherein the secondary amplifier is configured to define the input voltage. The device is configured to detect a difference in operating current between the primary and secondary amplifiers, and to compensate for any operational load that may be applied to the primary amplifier during operation.

Abstract: A circuit is provided having a secondary semi-analog FIR filter connected to a primary filter via a coefficient to reduce the size of the sizes of the resistors used in the primary filter. The coefficient may be one or more intermediate resistors connected between separate resistor/voltage driver banks that make up the FIR filter. The result is a circuit that takes up less chip space required to accommodate the required resistance for a digital to analog converter (DAC). The invention configures the resistor structure to produce the same output result as a conventional circuit, but with smaller resistor values that take up less surface area on the chip.

Abstract: An exemplary CMOS image sensor comprises a plurality of pixels arranged in an array. The plurality of pixels includes a first pixel proximate an optical center of the array, and a second pixel proximate a peripheral edge of the array. The CMOS image sensor further comprises a first metal interconnect segment associated with the first pixel situated in a first metal layer, and a second metal interconnect segment associated with the second pixel situated in the first metal layer. The second metal interconnect segment is shifted closer to the optical center of the array than the first metal interconnect segment so that the second metal interconnect segment approximately aligns with a principle ray angle incident the second pixel, thereby reducing pixel light shadowing.