Abstract: The present invention relates to multi-bit to pulse width modulated signal conversion, with extensions to digital-to-analog conversion. In particular, it has application to conversion of pulse code modulated signals, such as used in CDs and DVDs, to audio output.

Abstract: An improved semiconductor device that reduces reverse bias junction leakage in a photodiode by using a junction isolation region to isolate the photodiode from a trench isolation region. The improved semiconductor device improves image quality for different applications such as stand-alone digital cameras and digital cameras embedded in other imaging devices such as cellular phones and personal digital assistants.

Abstract: An improved semiconductor device that reduces reverse bias junction leakage in a photodiode by using a junction isolation region to isolate the photodiode from a trench isolation region. The improved semiconductor device improves image quality for different applications such as stand-alone digital cameras and digital cameras embedded in other imaging devices such as cellular phones and personal digital assistants.

Abstract: An image sensor acquires a preparatory image that is lighted for a predetermined preparatory duration by a strobe. The preparatory image data corresponding to the preparatory image from the image sensor is processed and an average preparatory image luminance is determined based on the preparatory image data and weighting at least a subset of the preparatory image data. A supplemental strobe duration is generated based on the average preparatory image luminance and luminance weightings. The electronic image sensor may be activated to acquire an image with supplemental light provided by the supplemental strobe duration.

Abstract: A system and method of operation of a power switching circuit is provided that includes a charging switch configured to be connected to an inductor at one node and configured to receive control signals to open and close the charging switch. The circuit further includes a first channel coupled to the one node with a first channel switch, configured to supply a first channel voltage, configured to operate in one of buck mode and boost mode and configured to receive control signals to open and close the first channel switch; and a second channel coupled to the one node with a second channel switch, configured to supply a second channel voltage, configured to operate in one of buck mode and boost mode and configured to receive control signals to open and close the first channel switch.

Abstract: There is provided a digital to an analog converter (DAC) comprising a current source, a first logic circuit, wherein the first logic circuit receives a first switching signal and a low-power mode signal, a first switch controlled by the first logic circuit, wherein the first switch selectively couples the current source to a ground in response to a signal from the first logic circuit, and a second switch controlled by a second switching signal, wherein the second switch selectively couples the current source to a load in response to the second switching signal. The first switching signal and the second switching signal may be complementary and are based on a digital signal that is being converted into an analog signal. The low-power mode signal is provided to selectively switch the DAC into a lower power consumption mode.

Abstract: A semiconductor imager chip is mated directly to a laminate-type substrate, such as a printed circuit board. A well is formed by placing a retaining wall on the printed circuit board around the imager chip. An optical material such as a clear polymer is injected into the well to cover the imager chip. After the clear polymer cures (hardens) the retaining wall may be removed. The optical material may also have light filtering or other optical properties in addition to transmissivity. The printed circuit board may have one or more layers. Some of such layers may comprise a ground-plane. High speed digital and analog lines may be strategically routed on the one or more layers to minimize interference with adjacent signal lines. Traditional sockets that receive ceramic or plastic chip carrier packages may be used in embodiments to receive the resultant printed circuit board based chip carrier. The circuit board may comprise a typical multi-component PCB or a chip-on-board carrier design.

Abstract: An adjustable lens system comprises a housing, an adjustable lens assembly, comprising a lens element, mounted to the housing and placeable in optical states, and a MEMS based micro-motor. The MEMS based micro-motor is mounted to the housing and is operably coupled to the lens assembly for movement of at least a portion of the lens assembly to change the optical state of the lens assembly.

Abstract: A memory control apparatus for block-matching motion estimation and an associated search pattern for processing video sequence in real-time are described in this disclosure. The motion estimation subsystem utilizes a set of memory banks to store a section of the reference picture used for computing the differences between an underlying block and a spatially shifted reference block. The memory control apparatus derives the memory addresses for storing the reference picture region in the memory banks in such a way that a row or a column of data from the reference block can be accessed in parallel without wait. The row- or column-data are then made available to the parallel computation unit for computing the block difference in a single processing cycle. An associated spiral search pattern that covers the whole search region is also described that minimizes the required data access and consequently saves power consumption.

Abstract: The disclosure is a solid-state imaging device, including a photosensor for collecting charge created by incident photons, a comparator for comparing a digital voltage value corresponding to the collected charge, to a predetermined value, and generating a comparison output, and a normalizing circuit for normalizing the digital voltage value, in response to the comparison output.

Abstract: A selectable resolution image capture system is provided having an array of photocells connected by a circuit that has a full-resolution and at least one low-resolution mode. The circuit converts electrical responses from the photocells, singly, or in grouped combinations, into digital signals. The circuit operates on both monochrome and color imagers. For monochrome imagers, a quarter-resolution mode is provided that renders the array of photocells into several four-contiguous-photocell blocks, and combines the electrical responses of the photocells of each block together. For color imagers, a quarter-resolution mode is provided that reads four same-colored photocells at a time using a one-step, three-step progression through the rows and columns of the photocell array. An image processor operates the circuit and a user interface permits a user to select between the full-resolution and low-resolution modes of the circuit to capture an image.

Abstract: An exemplary CMOS image sensor comprises a reset transistor, a photodiode, reset drain voltage circuitry, and reset gate voltage circuitry. A cathode of the photodiode is connected to a source of the reset transistor, and an anode of the photodiode is connected to ground. The reset drain voltage circuitry is connected to a drain of the reset transistor, and the reset gate voltage circuitry is connected to a gate of the reset transistor. During an exemplary hard reset operation, the reset drain voltage circuitry supplies a first drain voltage to the drain of the reset transistor in accordance with a determined level of light for exposure, which is determined dynamically. According to another exemplary reset operation, a hard reset phase is immediately followed by a soft reset phase.

Abstract: A sensor may be formed with a transistor comprising a gate that has both n-type and p-type regions to increase the gate work function. In combination with moving the p-type well such that the p-type well only partially dopes the channel of the transistor, the increased gate work function further increases the reset voltage level required to create the reset channel without having to use high doping levels in the critical regions of the sensor structure including the photo-detector and the reset transistor. The source of the reset transistor is partially beneath the n-type region of gate, while the transistor's drain is partially beneath the p-type region of the gate. The channel has a p-type well portion and a substrate portion. This construction of the sensor may eliminate the reset noise associated with the uncertainty of whether the charge left in the transistor's channel will flow back towards the photo-detector after the transistor has been turned off.

Abstract: Digital image enhancement techniques and apparatus are provided that increase the effective resolution of a digital imager without requiring an increase in the number of pixel sensors in the digital imager. Multiple images are captured in succession from the digital imager. The multiple images are compared in order to determine a correlation between the pixels of each image and the pixels of each of the other images. Two or more of the multiple images are employed to produce a single image of greater resolution than the resolution of any single image alone.

Abstract: A pixel correction system is provided. The pixel correction system includes a dynamic range detection system that receives test pixel data and adjacent pixel data and determines whether the test pixel data is within minimum pixel characteristic data and maximum pixel characteristic data of the adjacent pixel data. For example, if the pixel characteristic data is intensity, the dynamic range detection system detects bad pixels by identifying those pixels having an intensity value that is greater than the maximum intensity value of an adjacent pixel, or less than the minimum intensity value of an adjacent pixel.

Abstract: An electronic filter operates as a correlator that provides a discrete approximation of an analog signal. The analog to digital conversion is integrated directly approximation calculation. An array of sample and hold circuits or single bit comparators provide outputs to a series of multipliers, the other input of which is a coefficient value of a Fourier series approximation of the desired frequency response. Each of the sample and hold circuits samples sequentially in time and holds its sample until the next cycle. Thus the sample point rotates in time through the array and each new sample is multiplied by a different coefficient. The output of the multipliers is summed for evaluation.

Abstract: The present invention relates to a signal processor and methods of using a signal processor. In one aspect, the present invention relates to a signal processor that includes a pulse width modulator having a clock rate, and also includes a digital filter configured to receive an output of the pulse width modulator, wherein the digital filter samples the output at the clock rate to suppress the distortion. In another aspect, the present invention relates to a method including modulating a first pulse code modulated signal having a first resolution into a second pulse code modulated signal having a second resolution that is smaller than the first resolution. This aspect further includes modulating the second pulse code modulated signal into a third signal that includes a plurality of pulses in time having a clock rate, and filtering in a digital domain the plurality of pulses in time to suppress a distortion in the third signal.

Abstract: An imaging system is provided to minimize pixel defects by capturing an image in the spatial frequency domain. An image processor receives the spatial frequency-domain image data from the imager and transforms the frequency-domain image data into spatial-domain image data. To capture the image in the spatial frequency domain, an optical lens is placed between a spatial representation of an image object and the imager. The optical lens performs an approximate Fourier transform on light emanating from the spatial representation of the image object toward the imager. The image processor performs an approximate inverse Fourier transform on the data received from the imager, restoring the spatial representation of the image.

Abstract: An image sensor and method is provided to improve the measurement of a dark signal reference while substantially suppressing radiation charges that enter an active area of the image sensor from reaching a shielded dark signal detector. In one implementation, dark signal detector is shielded and separated from the active area to substantially reduce the radiation charges that reach the dark signal detector. In another implementation, the image sensor includes a radiation guard that is disposed between the active area and the shielded detector. When radiation or light is permitted to enter the active area, the guard when adequately biased attracts and collects radiated charges that may otherwise travel beyond the active area to reach the shielded detector and contaminate a measurement for the dark signal reference.

Abstract: Methods, apparatus, and systems are presented for arbitrating access to a shared resource involve deciding whether to grant access to the shared resource to at least one of a first plurality of devices in accordance with a first arbitration algorithm and deciding whether to grant access to the shared resource to at least one of a second plurality of devices in accordance with a second arbitration algorithm distinct from the first arbitration algorithm, if access to the shared resource is not granted to at least one of the first plurality of devices. Arbitration algorithms that may be used as the first and/or second arbitration algorithm include fixed-priority algorithms, round-robin algorithms, and most-recently-used algorithms. In accordance with one embodiment, at least one of the first and second arbitration algorithms is implemented in hardware adapted to switch from executing one arbitration algorithm to executing another arbitration algorithm in one clock cycle.