Abstract: A system and method of generating a clock signal are provided for driving a plurality of consecutive circuit phase operations. The method includes generating a clock signal, transmitting the clock signal to one circuit phase operation, and transmitting another clock signal to a previous circuit phase operation. A circuit configured according to the invention can clock a plurality of consecutive circuit phase operations with a single master clock, where each circuit phase generates a clock signal to clock a previous phase, obviating connections from a master clock to multiple phases.

Abstract: The invention is directed to a bi-quad filter circuit configured with sigma-delta devices that operate as binary rate multipliers (BRMs). Unlike conventional bi-quad filter circuits, the invention provides a bi-quad filter configured with a single-bit BRM. In another embodiment, the invention further provides a bi-quad filter configured with multiple-bit BRMs.

Abstract: A differential input flash analog-to-digital converter in which an array of comparators is connected to compare reference signals within a parabolic distribution of such signals generated by the application of a differential input signal across an impedance network. Preferably, the comparator array comprises at least two pluralities of comparators, the first plurality of comparators comparing pairs of reference nodes separated by a first step size, and the second plurality of comparators comparing pairs of reference nodes separated by a second step size. Even more preferably, the comparator array further comprises a third plurality of comparators comparing pairs of reference nodes separated by a third step size, but only where necessary to maximize the available comparison range of the converter. The flash converter according to the invention provides increased gain from input without accumulation of comparator input currents and without sacrificing the number of actual comparisons of reference signals.

Abstract: A system for generating image conversion data is provided. The system includes a numerator buffer storing numerator data of a conversion ratio, such as where the numerator of the ratio represents the relative current size of a set of image data and the denominator of the ratio represents the relative size of the target set of image data. A denominator buffer stores denominator data of the conversion ratio. A pixel sample control system receives the numerator data and the denominator data and generates pixel sample control data that is used to select a pixel from a pixel data stream, such as to allow a pixel dropping sequence or a pixel duplication sequence to be generated based on the values stored in the numerator buffer and the denominator buffer.

Abstract: A circuit is provided to correct a sample rate by way of time domain interpolation having a first circuit loop having an up/down counter configured to receive an input signal and a feedback signal and an adder configured to receive the output signal from the up/down counter and to output a carry output as the feedback signal to the up/down counter and a second circuit loop configured to transmit a sum output from the adder to a modulator and to feed back an output signal from the modulator to an input of the adder.

Abstract: The present invention relates to timeshifting of program content. In particular, it relates to using an external memory element, thereby reducing the cost of the device that uses timeshifting.

Abstract: An electronic imaging device includes a photosensor having a plurality of photodetectors in an array structure, and a processor in signal communication with the photodetectors. The processor is operable to cross-talk adjust a signal from a photodetector based upon the value of the signal from that photodetector and signals from photodetectors adjoining that photodetector.

Abstract: A system and method are provided for performing a spread spectrum clock generation, where the system includes self-adjusting delay line configured to spread the spectrum of a fixed circuit using a fixed clock frequency and a delay circuit configured to generate an adjustment signal to the delay line by adding or subtracting an addition delay per cycle, therefore causing a shift in the output clock frequency, wherein the amount of shift is proportional to the rate of addition or subtraction of delay.

Abstract: A system and related method are provided for producing a reference bias current that varies within a limited threshold from its nominal value based on band gap voltage, and that generates the bias current substantially independent from process and temperature. In one embodiment, the invention provides a process dependant voltage generator, a temperature independent voltage generator, and a voltage to current converter receiving inputs from bandgap voltage generator and a temperature independent voltage generator to generate a bias current that is substantially independent from process and temperature.

Abstract: An electronic device is provided such as a programmable rise/fall time control circuit, for example, that delivers a continuous and near linear rising/falling slope of a control signal, with programmability that can be implemented in future CMOS image sensor devices. This device includes a programmability block for reset or transfer gate signals. The programmability block includes two inputs: an input bias current and a signal from the control bits. The programmability block further includes two similar internal circuit blocks, one for generating a fall time control signal, and one for generating a rise time control signal. Additionally the programmability block includes two outputs; a fall time control signal, and a rise time control signal. The device further includes a reset or transfer gate buffer configured as an inverter. The reset or transfer gate buffer includes three input signals: The fall time control signal and rise time control signal from the programmability block, and an INT Reset signal.

Abstract: A system and method are provided for producing two asymmetric duty cycle clock phases as outputs, where the duration of the active phase may be varied to generate clock signal having an asymmetric duty cycle. A circuit configured according to the invention includes a monostable clock generator configured to produce an asymmetric duty cycle clock phase from a reference clock input, a delayed phase generator configured to produce two clock phases whose falling edges are delayed with respect to the input signals, and a second phase generator configured to produce a second asymmetric duty cycle clock phase. The phase may be programmable by including a variable resistor network that can be varied in response to control signals.

Abstract: A device and method are provided for implementing digital baseband separation of composite video signals with reduced memory requirements. The method and device require that only the composite signal be stored in a large delay element. Multiple quadrature demodulators are employed to generate multiple delayed complex baseband signals. Therefore, no large complex baseband delay element is required.

Abstract: The present invention relates to a signal processor and methods of using a signal processor. In one aspect, the present invention relates to a signal processor that includes a pulse width modulator having a clock rate, and also includes a digital filter configured to receive an output of the pulse width modulator, wherein the digital filter samples the output at the clock rate to suppress the distortion. In another aspect, the present invention relates to a method including modulating a first pulse code modulated signal having a first resolution into a second pulse code modulated signal having a second resolution that is smaller than the first resolution. This aspect further includes modulating the second pulse code modulated signal into a third signal that includes a plurality of pulses in time having a clock rate, and filtering in a digital domain the plurality of pulses in time to suppress a distortion in the third signal.

Abstract: A system and method are provided for generating accurate coefficients in a binary rate multiplier by signaling an enabling circuit to generate an enabling signal to the binary rate multiplier such that the average effect of the factored output signal corresponds to a signal multiplied by a predetermined coefficient value; where the system multiplies a signal by a plurality of factors in response to the enabling signal, where the smallest exponent of two is determined that is greater than the factor desired; and the desired factor is divided by the smallest exponent to generate a resulting fraction that is the duty cycle of the enabling signal.

Abstract: The present invention relates to digital-to-analog conversion. In particular, it has application to conversion of pulse code modulated signals, such as used in CDs and DVDs, to a pulse width modulated or analog signal.

Abstract: A method for noise removal filtering is provided. The method includes selecting a characteristic of a test pixel, such as brightness, and comparing the brightness of the test pixel to the brightness of an adjacent pixel. The noise removal filtering is terminated if the test pixel brightness is equal to the adjacent pixel brightness, such that it can be determined that the test pixel has not been corrupted with noise data.

Abstract: An integrated circuit having a signal generator for generating an oscillating signal and a second element utilizing the oscillating signal. The signal generator is a ring oscillator having an odd number of active elements connected in series, where the signal output of one active element is connected to the signal input of the next active element to form a closed ring of active elements. Each active element has a power supply input and a ground connection, a signal input and a signal output, an inverter sub-element having a pair of current mirrors, and a capacitor controlled bias sub-element.

Abstract: A ring oscillator having an odd number of active elements connected in series, where the signal output of one active element is connected to the signal input of the next active element to form a closed ring of active elements. Each active element has a power supply input and a ground connection, a signal input and a signal output, an inverter sub-element having a pair of current mirrors, and a capacitor controlled bias sub-element.

Abstract: A system and corresponding method is provided for digitally controlling the volume of an audio signal having a series of arithmetic units configured with combinatorial logic to operate in response to control signals to produce a digital output signal amplified in a predetermined manner to digitally control the volume.

Abstract: To encode an unencoded block of a frame, a search window is defined within the frame. Each pixel disposed within the search window and disposed in the unencoded portion of the frame that is assigned a value. A difference is computed between the unencoded block and each possible block within the search window. The block having the smallest difference, together with this difference are used to encode the unencoded block.