Abstract: A mask for a semiconductor process step includes an indicia section. The indicia section on the mask is used to produce a field of separated polygon elements with a defined negative space in the field providing an indicia.

Abstract: A device demultiplexes an optical signal to produce a number of client streams for client devices. The device produces overhead packets for the client devices. The overhead packets are sent using a packet interface on the device. The overhead packets are sent to the client devices with a Virtual Local Area Network Identification (VLAN ID) portion of the overhead packets identify a client device of the client devices.

Abstract: A two chip network adapter is used to implement offloaded networking tasks. The first chip is the main ethernet controller chip. The second chip implements the offloaded tasks. Communication between a host and the second chip is done by adding offload and completion tags to the ethernet frame header of frames associated with the offloaded networking task.

Abstract: At a generator, frame events are received indicative of frame boundaries. The amount of client data received between frame events is counted to get a raw count. The raw count is low-pass filtered to get a smoothed value. At a receiver, an indication of the smoothed count is received from the generator; and the indication is smoothed using a low-pass filter and used to produce a client data rate.

Abstract: 10 bit words from a client are packed into 64B/65B blocks such that at least some of the blocks have data containing only a portion of at least some of the 10 bit words. The 64B/65B blocks are combined into groups of eight to form superblocks. The superblocks are combined in multiples of five to form a Generic Framing Procedure (GFP) frame such that the GFP frame contains an integer number of complete 10 bit words with no partial 10-bit words.

Abstract: Used bandwidth counts for each of multiple client streams are maintained. A used bandwidth count for a client stream is increased when data from the client stream is put in a Generic Framing Procedure (GFP) frame onto the GFP path and is decreased once every time period by allocated bandwidth credits value. The used bandwidth count for a client stream is compared with a bandwidth limit before sending data in the client stream in a GFP frame onto the GFP path.

Abstract: A method for improving heavy-to-light load transient response in low-power switch-mode power supplies is described. It uses a negative voltage input power rail and a digital controller with an extended duty ratio control value to provide faster discharging current slew rate in the switched mode power supplies (SMPS) inductor.

Abstract: A multiphase controller for a DC-to-DC power supply includes logic to estimate parameters for multiple phases that provide a combined output at a load. The estimated parameters include a current estimate and an effective resistance estimates for each phase so that a power estimate for each phase can be produced. The logic adjusts the operation of the phases using the power estimate for each phase.

Abstract: A digital pulse controller uses digital logic to send pulses to a high side and low side switches of a switch-mode power supply converter. The digital logic uses a pulse frequency mode which includes a frequency targeting mode and an ultrasonic mode. The frequency targeting mode dynamically adjusts the size of the pulses in order to achieve a switching frequency within a desired band. The ultrasonic mode is switched into when the frequency of the pulses are at or below a threshold and the time of the pulses reaches a minimum threshold.

Abstract: A Digital-to-Analog Converter (DAC) produces an analog reference value from a first reference input. The analog reference value and an output value are used to produce an analog error signal. An Analog-to-Digital Converter (ADC) converts the analog error signal to a digital value. The ADC has higher level of resolution than the DAC. An error encoder adjusts the digital value to produce a digital error value using a second reference input.

Abstract: A method includes aligning a reference window and target window for compression of a target data stream in terms of a reference data stream. The anchors are determined by examining the target data stream and reference data streams. The target data stream is aligned with respect to the reference data streams using the anchors. Pattern matching between the aligned target data stream and reference data stream is done to delta compress the target data stream.

Abstract: Logic to indicate a revision level includes multiple cells for one bit of the revision level. The cells being wired to be a pass-through cell or a swap cell during fabrication. At least some of the cells are such that to change the bit of the revision level, it is sufficient to change any single mask of a group of masks. The change to the single mask switches at least one of the cells from pass-through cell to a swap cell, or vice-versa.

Abstract: A controller produces high-side and low-side control signals. The high and low-side signals are used to switch high-side and low-side transistors in the power stage to control the voltage across the power stage output capacitor of the power stage. A boost feedback charge pump receives the low or high-side signal to increase the charge on a charge pump output capacitor. The controller is configured to send Pulse Frequency Modulation (PFM) high and low-side signals that control the voltage on the power stage output capacitor and charge the charge pump output capacitor. The controller is also configured to send boost feedback (BFB) high and low-side signals that charge the boost feedback capacitor, but are designed to not significantly change the charge on the power stage output capacitor.

Abstract: A system for deduplicating data comprises a card operable to receive at least one data block and a processor on the card that generates a hash for each data block. The system further comprises a first module that determines a processing status for the hash and a second module that discards duplicate hashes and their data blocks and writes unique hashes and their data blocks to a computer readable medium. In one embodiment, the processor also compresses each data block using a compression algorithm.

Abstract: Packets are processed while maintaining a sequence of the packets. Packets are received and a sequence identifier assigned to the packets. The sequence identifier specifies a serial order associated with the packet. The packets are provided to a plurality of parallel packet transform processors and the packets are processed utilizing the packet transform processors. The processed packets are ordered based on the sequence identifier of the packets. The packets may be evaluated to classify the packets so as to identify related packets. A sequence identifier is assigned to the packets such that the sequence identifier identifies an ordering of the related packets. The processed packets are ordered based on the classification of the packets and the sequence identifier of the packets. Parallel packet transform processing may be particularly well suite to parallel cryptographic processing.

Abstract: The present invention uses a reference voltage that varies within a Pulse Width Modulation (PWM) cycle to generate the PWM signal. This allows for stability in the feedback of Constant On-Time (COT) control for buck controllers when low Equivalent Series Resistance (ESR) capacitors are used as the output capacitor. The reference voltage is adjusted using features of a PWM cycle in a voltage mode without using external inductor current information.

Abstract: Digital logic receives a gapped and jittery clock signal with specified frequency and frequency offset allowed by specification and a reference clock signal with same specified frequency and different frequency offset allowed by specification having low jitter. The digital logic adds and/or removes cycles from the reference clock signal over an extended period of time to produce a produced clock signal with low jitter that has a frequency that approaches the frequency of the gapped and jittery clock signal. The produced clock signal being provided as feedback to the digital frequency comparator and also acts as final dejitter smooth clock output with 50% duty cycle.

Abstract: One embodiment of the present invention is a digitally controlled DC-DC converter comprising of a power stage including at least one switch and an output capacitor. A digital controller can control the switching of the at least one switch. The digital controller can include logic to produce an indication related to a zero resulting from the equivalent series resistance (ESR) of the output capacitor and to update the control of the switching of the switch in the power stage based on the estimate.

Abstract: An open-drain output buffer is operative to sustain relatively high voltages applied to an output pad. The open-drain buffer includes a number of floating wells, output switching devices and corresponding well-bias selectors to ensure that no gate oxide sustains voltages greater than a predefined value. PMOS and NMOS well-bias selectors operate to select and provide an available highest or lowest voltage, respectively, to bias corresponding well-regions and ensure no device switching terminals are electrically over stressed. As output related terminals experience switching related voltage excursions, the well-bias selectors select alternate terminals to continue selection of the respective highest or lowest voltages available and provide correct well-biasing conditions. Voltage dividers are incorporated to generate well-biasing control voltages.

Abstract: A switched mode power can use a digital controller to control the switching of the at least one switch of the switched mode power supply. The current through the power inductor can be estimated using a self-tuning digital current estimator.