Abstract: A practical method and system for oversampled digitally controlled DC-DC converters is presented. To minimize the switching losses while maintaining all advantages of the oversampling, “glue logic” and application specific oversampling digital pulse-width modulator are introduced. Experimental results demonstrate transient response with 50% smaller deviation than that of conventional controllers, allowing for proportional reduction in the size of the power stage output capacitor.

Abstract: A virtual block device is an interface with applications that appears to the applications as a memory device, such as a standard block device. The virtual block device interacts with additional elements to do data deduplication to files at the block level such that one or more files accessed using the virtual block device have at least one block which is shared by the one or more files.

Abstract: A method for improving heavy-to-light load transient response in low-power switch-mode power supplies is described. It uses a negative voltage input power rail and a digital controller with an extended duty ratio control value to provide faster discharging current slew rate in the switched mode power supplies (SMPS) inductor.

Abstract: A practical method and system for oversampled digitally controlled DC-DC converters is presented. To minimize the switching losses while maintaining all advantages of the oversampling, “glue logic” and application specific oversampling digital pulse-width modulator are introduced. Experimental results demonstrate transient response with 50% smaller deviation than that of conventional controllers, allowing for proportional reduction in the size of the power stage output capacitor.

Abstract: A multichannel digital pulse width modulator/digital pulse frequency modulator uses a single ring oscillator that is shared by multiple channels. The ring oscillator has taps that can be used for least significant bit (LSB) precision of the generated PWM signal. The ring oscillator also produces a ring clock that is used to synchronize logic in the channels. Since the logic in the channels are synchronized by the ring clock, the channels can each independently produce different frequency PWM (or PFM) signals and still share the same ring oscillator.

Abstract: Logic to indicate a revision level includes multiple cells for one bit of the revision level. The cells being wired to be a pass-through cell or a swap cell during fabrication. At least some of the cells are such that to change the bit of the revision level, it is sufficient to change any single mask of a group of masks. The change to the single mask switches at least one of the cells from pass-through cell to a swap cell, or vice-versa.

Abstract: An electrostatic discharge protection device is disposed between true-complement input pins of a differential signal pair and a ground node. A common node couples the three diode stacks together. A first and a second diode stack each connect to one of the differential signal pair input pins. The third diode stack couples to the ground node. Each of the diode stacks is fabricated by a pair of high concentration p-type contact dopant regions within a low concentration n-well region. Each of the p-type contact dopant regions is configured to form back-to-back diodes connected in series with cathodes in common. In protecting common mode receivers, current from an ESD event is channeled to ground rather than to the complementary receiver node. The diode stacks are capable of withstanding a 15 kV incident and save up to 25% in area compared to a fully parallel configuration for differential signal pairs.

Abstract: A multiple channel Digital Pulse Width Modulator (DPWM) can include a single delay locked loop with a delay line, the delay line producing a number of outputs. Circuitry can use a delay line mask to mask a portion of the delay line outputs to produce a modified outputs so as to prevent premature pulse width reset. Jitter tolerance look ahead circuits can prevent jitter from causing premature reset of pulse width modulated signals. The pulse width modulators can include multiple alternately used multiplexers so that the operation of the pulse width modulators is not affected by the load time of the multiplexers.

Abstract: One embodiment of the present invention is a Gray code current-mode analog to digital (ADC) converter using a Gray code current-mode ADC building block. The Gray code current-mode ADC building block can produce a Gray code bit and a current output that is sent to a next Gray code ADC building block. In one embodiment, the Gray code current-mode ADC building block does not use a voltage comparator in a signal path of the current output. In one embodiment, an 8 bit analog-to-digital converter can have a 65 ns conversion time and consume only 10 mW of power with a single +5.0V supply.

Abstract: A voltage signal is monitored in comparison to another voltage signal by a differential amplifier. When the first voltage signal value drops below the second voltage signal value an output signal is boosted in response. The output signal returns to a previous state without boost.

Abstract: A system and method for storing encrypted electronic data using a transmission Control Protocol (TCP), requires leaving both the header and the first 48 bytes of the “0” data packet in the data area of the TCP format in clear text. Consequently, the data can be routed to a main address (storage facility), and then to a sub-address (storage device) for storage. A single compression/encryption operation can be accomplished, before storage, at the host (server), the network switch, or the final storage device.

Abstract: The separate high speed and full speed drivers used in a Universal Serial Bus 2.0 application can be combined into one driver which functions both as full speed/high speed driver and as a result provides output impedance for the full speed/high speed modes which is less process dependent.

Abstract: An encapsulation packet is received as a sequence of parallel data segments. First information within the encapsulated packet is obtained based on second information indicative of a location of the first information within the encapsulated packet. The encapsulating header is modified based on the first information.

Abstract: A charge pump is configured to control current flow at an output node in response to input signals. A plurality of control signals are generated based upon the input signals. The control signals operate to control the timing and duration of current flows within the charge pump and to thereby reduce charge pump power consumption. Based upon the control signals, the conductivity of a first path between a power supply and the output node and a second path between the output node and a ground potential is varied. Optionally, the charge pump is disposed as part of a phase-locked loop (PLL), the input signals are produced by a phase/frequency detector, and current flow at the output node controls an oscillator element.

Abstract: A multiphase hybrid digital pulse width modulator can comprise a counter that is selectable between at least two different numbers of states to indicate a first portion of a switching period. Unclocked logic can indicate a second portion of the switching period. The unclocked logic can include a delay line.

Abstract: A PLL includes control circuitry adapted to detect missing pulses of a reference clock and to control an output voltage of a charge pump disposed in the PLL accordingly. A signal generated in response to the detection of a missing pulse is pulse-width limited and applied to the charge pump during a first period. The detection of the pulse-width limited signal is used to generate a first slew signal that is also pulse-width limited and applied to the charge pump during a second period. The detection of the first slew signal is used to generate a second slew signal that is also pulse-width limited and applied to the charge pump during a third period. The amount of current supplied by the charge pump during the second charging period is equal to a sum of currents withdrawn by the charge pump during the first and third time periods.

Abstract: A frame delineation mechanism which alternately considers even and odd sync pattern position possibilities. With the addition of toggle logic, each of 66 possible states of even and odd alignment are exhausted in turn, odd, followed by even, followed by odd and so on, providing synchronization more quickly than known mechanisms. Additionally, faster convergence is reached due to the use of an exhaust register which keeps track of those alignment states that were tested but did not provide synchronization. Until synchronization is acquired, the states indicated in the exhaust register are ignored in further attempts to acquire synchronization.

Abstract: An auto-detecting input circuit is operative to sustain relatively high voltages applied to an input pad and generate corresponding signal levels at a native supply voltage range. The input circuit includes floating wells, corresponding bias selectors, and input biasing transistors to ensure that no gate oxide exposed to external voltages sustains a voltage greater than a predefined value. Bias selectors select an available highest voltage to reverse bias corresponding floating wells and ensure transistors are not electrically overstressed. As input-related terminals experience switching related voltages, the bias selectors select alternate terminals to continue selection of the highest voltage available and provide correct reverse biasing conditions. A resistor and clamp generate translated output voltage levels limited to the native supply voltage range. A latch is triggered by a first input signal excursion above the native supply voltage.

Abstract: A circuit with an input acquisition loop and an output acquisition loop is used to compensate for the input offset voltage and bias current errors of an operational amplifier.

Abstract: A phase/frequency locked loop (PLL) includes circuitry adapted to detect missing pulses of a reference clock and to control the phase bump of the PLL. The circuitry includes, in part, first and second flip-flops, as well as a one-shot block. The first flip-flop has a data input terminal responsive to a voltage supply, and a clock terminal responsive to an inverse of feedback clock. The second flip-flop has a data input terminal responsive to an output of the first flip-flop, and a clock terminal responsive to the inverse of the feedback clock. The one-shot block generates a pulse in response to a rising edge of the reference clock that is used to generate the feedback clock. The one-shot block generates an output signal applied to a reset terminal of the first flip-flop.