Abstract: Embodiments of the present invention concern a multiphase switch-mode power supply. The multiple phase switch-mode power supply can have at least one switch and a digital controller to control the switching of the at least one switch. During a calibration period, the digital controller can freeze the current of all of the multiple phases except for a phase being calibrated. This can be done by fixing the current reference of the phases except for the phase being calibrated.

Abstract: A multiphase hybrid digital pulse width modulator can comprise a counter that is selectable between at least two different numbers of states to indicate a first portion of a switching period. Unclocked logic can indicate a second portion of the switching period. The unclocked logic can include a delay line.

Abstract: An open-drain output buffer is operative to sustain relatively high voltages applied to an output pad. The open-drain buffer includes a number of floating wells, output switching devices and corresponding well-bias selectors to ensure that no gate oxide sustains voltages greater than a predefined value. PMOS and NMOS well-bias selectors operate to select and provide an available highest or lowest voltage, respectively, to bias corresponding well-regions and ensure no device switching terminals are electrically over stressed. As output related terminals experience switching related voltage excursions, the well-bias selectors select alternate terminals to continue selection of the respective highest or lowest voltages available and provide correct well-biasing conditions. Voltage dividers are incorporated to generate well-biasing control voltages.

Abstract: One embodiment of the present invention is a digitally controlled DC-DC converter comprising of a power stage including at least one switch and an output capacitor. A digital controller can control the switching of the at least one switch. The digital controller can include logic to produce an indication related to a zero resulting from the equivalent series resistance (ESR) of the output capacitor and to update the control of the switching of the switch in the power stage based on the estimate.

Abstract: A multiple channel Digital Pulse Width Modulator (DPWM) can include a single delay locked loop with a delay line, the delay line producing a number of outputs. Circuitry can use a delay line mask to mask a portion of the delay line outputs to produce a modified outputs so as to prevent premature pulse width reset. Jitter tolerance look ahead circuits can prevent jitter from causing premature reset of pulse width modulated signals. The pulse width modulators can include multiple alternately used multiplexers so that the operation of the pulse width modulators is not affected by the load time of the multiplexers.

Abstract: A digital controller for dc-dc switching converters can operate under light load conditions. The controller can be suitable for the use in switch-mode power supplies providing regulated output voltage for handheld devices and other low-power electronics. To create long time intervals, compared to the propagation time of digital logic a DPFM/DPAM can use a ring oscillator with two sets of delay cells and two signals racing around the ring.

Abstract: A low-power digital pulse-width modulator (DPWM) architecture for high frequency dc-dc switch-mode power supplies (SMPS) is disclosed that is well-suited for integration in power management systems of small handheld devices. The DPWM can operate in a stand-alone mode, without external clock, and can be implemented on a portion of silicon area needed for other DPWM solutions. In addition it has low power consumption and provides a good linearity of the input-to-output characteristic, also not characteristic for other architectures.

Abstract: A communications system comprising a segmenting mechanism configured to receive a plurality of payloads and divide each of the received payloads into segments, a framing mechanism configured to insert at least one of the segments from each of the plurality of payloads into a packet, a first interface configured to transmit the packet, and a second interface configured to transmit segment information about the segments in the packet.

Abstract: A switching voltage regulator includes, in part, N output stages, a loop ADC, a multiplexer, a current ADC, and an interrupt block. The loop analog-to-digital converter receives the N output voltages each of which is associated with one of N channels. The loop ADC is adapted to vary a duty cycle of N signals each applied to one of the N output stages that generate the N output voltages. The interrupt block is adapted to enable the multiplexer to couple an output stage to the current ADC if a difference between voltages sensed at an output stage during at least two sampling times exceeds a predefined threshold value. The interrupt block may also be adapted to enable the multiplexer to couple an output stage to the current ADC block if a difference between a voltage sensed at the output stage and a reference voltage exceeds a predefined threshold value.

Abstract: To maintain the amplitude of an oscillating signal within a defined range, the detected peak level of the oscillating signal is compared to a reference voltage. If the detected peak level is determined as being greater than the reference voltage, the common source/drain voltage of a differential amplifier driving the crystal oscillator across its input terminals is reduced so as to lower the amplitude of the oscillation signal. If the detected peak level is determined as being smaller than the reference voltage, the common source/drain voltage of the differential amplifier driving the crystal oscillator is increase so as to raise the amplitude of the oscillation signal.

Abstract: An open-drain output buffer is operative to sustain relatively high voltages applied to an output pad. The open-drain buffer includes a number of floating wells, output switching devices and corresponding well-bias selectors to ensure that no gate oxide sustains voltages greater than a predefined value. PMOS and NMOS well-bias selectors operate to select and provide an available highest or lowest voltage, respectively, to bias corresponding well-regions and ensure no device switching terminals are electrically over stressed. As output related terminals experience switching related voltage excursions, the well-bias selectors select alternate terminals to continue selection of the respective highest or lowest voltages available and provide correct well-biasing conditions. Voltage dividers are incorporated to generate well-biasing control voltages.

Abstract: One embodiment of the present invention is a Gray code current-mode analog to digital (ADC) converter using a Gray code current-mode ADC building block. The Gray code current-mode ADC building block can produce a Gray code bit and a current output that is sent to a next Gray code ADC building block. In one embodiment, the Gray code current-mode ADC building block does not use a voltage comparator in a signal path of the current output. In one embodiment, an 8 bit analog-to-digital converter can have a 65 ns conversion time and consume only 10 mW of power with a single +5.0V supply.

Abstract: A multiphase hybrid digital pulse width modulator can comprise a counter that is selectable between at least two different numbers of states to indicate a first portion of a switching period. Unclocked logic can indicate a second portion of the switching period. The unclocked logic can include a delay line.

Abstract: A voltage-to-time based windowed analog-to-digital converter (ADC) can have programmable reference voltage, conversion time, and accuracy of voltage regulation. The ADC can be fully implemented on a small silicon area and is suitable for implementation in various integrated digital controllers for high-frequency low-power switch-mode power supplies (SMPS). The programmable characteristics can be achieved through the utilization of the inherent averaging effect of the delay line or of the other voltage-to-time conversion structures and through the adjustments of delay cells' propagation times or the effective voltage-to-time conversion ratio in alternative structures.

Abstract: A phase/frequency locked loop (PLL) includes circuitry adapted to detect missing pulses of a reference clock and to control the phase bump of the PLL. The circuitry includes, in part, first and second flip-flops, as well as a one-shot block. The first flip-flop has a data input terminal responsive to a voltage supply, and a clock terminal responsive to an inverse of feedback clock. The second flip-flop has a data input terminal responsive to an output of the first flip-flop, and a clock terminal responsive to the inverse of the feedback clock. The one-shot block generates a pulse in response to a rising edge of the reference clock that is used to generate the feedback clock. The one-shot block generates an output signal applied to a reset terminal of the first flip-flop.

Abstract: A SONET signal is terminated by pointer processing a physically concatenated SONET signal to output a pointer processed physically concatenated SONET signal. Virtual concatenation-related byte markers (for example, H4 and J1) are then inserted into the pointer processed physically concatenated SONET signal. Virtual concatenation overhead data (for example, MFI and SEQ#) is then inserted into the pointer processed physically concatenated SONET signal so as to produce a converted virtually concatenated SONET signal. Virtual concatenation logic processing is then performed on the converted virtually concatenated signal. In this way, a physically concatenated SONET signal can be received and processed on a single integrated circuit with a virtual concatenation logic processor receiver this obviating the need for including a separate physically concatenated logic processing receiver or multiple integrated circuit chips.

Abstract: A voltage signal is monitored in comparison to another voltage signal by a differential amplifier. When the first voltage signal value drops below the second voltage signal value an output signal is boosted in response. The output signal returns to a previous state without boost.

Abstract: A switching voltage regulator includes, in part, N output stages, a loop ADC, a multiplexer, a current ADC, and an interrupt block. The loop analog-to-digital converter receives the N output voltages each of which is associated with one of N channels. The loop ADC is adapted to vary a duty cycle of N signals each applied to one of the N output stages that generate the N output voltages. The interrupt block is adapted to enable the multiplexer to couple an output stage to the current ADC if a difference between voltages sensed at an output stage during at least two sampling times exceeds a predefined threshold value. The interrupt block may also be adapted to enable the multiplexer to couple an output stage to the current ADC block if a difference between a voltage sensed at the output stage and a reference voltage exceeds a predefined threshold value.

Abstract: A switched mode power can use a digital controller to control the switching of the at least one switch of the switched mode power supply. The current through the power inductor can be estimated using a self-tuning digital current estimator.

Abstract: Methods are disclosed for performing analog to digital signal conversion in shorter time and/or with less power consumption. A predictive guess is supplied as a digital first signal. The digital first signal is converted (D/A) to a counterpart, analog guess signal. A comparison is made between the analog guess signal and a received, analog input sample signal. The result of the comparison is used to improve on the initially supplied guess in a next cycle. Fewer cycles and less power is consumed if the initial guess is within a certain range of the actual magnitude of the analog input sample signal.