Abstract: A 3D device, the device including: at least one first level including logic circuits; at least one second level bonded to the first level, where the at least one second level includes a plurality of transistors; connectivity structures, where the connectivity structures include a plurality of transmission lines, where the plurality of transmission lines are designed to conduct radio frequencies (“RF”) signals, and where the bonded includes oxide to oxide bond regions and metal to metal bond regions; and a plurality of vias disposed through the at least one second level, where at least a majority of the plurality of vias have a diameter of less than 5 micrometers.

Abstract: A semiconductor device, the semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 240 nm alignment error; where the fifth metal layer includes global power delivery; and a via disposed through the second level, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.

Abstract: A semiconductor device including: a plurality of transistors, where at least one of the transistors includes a first single crystal source, channel, and drain, where at least one of the transistors includes a second single crystal source, channel, and drain, where the second single crystal source, channel, and drain is disposed above the first single crystal source, channel, and drain, where at least one of the transistors includes a third single crystal source, channel, and drain, where the third single crystal source, channel, and drain is disposed above the second single crystal source, channel, and drain, where at least one of the transistors includes a fourth single crystal source, channel, and drain, where the fourth single crystal source, channel, and drain is disposed above the third single crystal source, channel, and drain, and where the fourth drain is aligned to the first drain with less than 40 nm misalignment.

Abstract: A device, including: a first structure including first memory cells, the first memory cells including first transistors; and a second structure including second memory cells, the second memory cells including second transistors, where the second transistors overlay the first transistors, and a plurality of memory cells control lines, where the first transistors are self-aligned to the second transistors, where a second transistor channel of the second transistors is aligned to a first transistor channel of the first transistors, the aligned is at an atomic level as would have been resulted from an epitaxial growth process.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; a first oxide layer disposed over the second metal layer; a second oxide layer disposed over the first oxide layer; and a second level including at least one array of memory cells and second transistors, where each of the memory cells includes at least one of the second transistors, where the second level overlays the first level, where at least one of the second transistors includes at least two independent gates, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.

Abstract: A method of managing power usage of a depth imaging system including an image sensor having an array of pixels configured to detect light incident from a scene and an optical encoder configured to modulate the incident light detected by the pixels in accordance with an angle of incidence of the incident light. The method includes operating the system in a lower power mode corresponding to a first power consumption level, including capturing, with the pixels, image data of the scene having angle-dependent information encoded therein by the optical encoder, and identifying, based on the angle-dependent information, signature information in the image data indicative of a detection of an object within a specified depth range. The method also includes, in response to identifying the signature information, transitioning to operating the system in a higher power mode corresponding to a second power consumption level higher than the first power consumption level.

Abstract: 3D semiconductor device including: a first level including first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the first single-crystal transistors; a first metal layer disposed atop the first single-crystal transistors; a second metal layer disposed atop the first metal layer; a second level disposed atop the second metal layer includes second transistors and a memory array of first memory cells; a third level including second memory cells which include some third transistors, which themselves include a metal gate and is disposed above the second level; a third metal layer disposed above the third level; a fourth metal layer disposed above the third metal layer; a connective path from the third metal layer to the second metal layer with a thru second level via of a diameter less than 800 nm which also passes thru the memory array, memory control circuits for wear leveling.

Abstract: A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and is overlaying the first level; at least four electronic circuit units (ECUs); and a redundancy circuit, where each of the ECUs includes a first circuit which includes a portion of the first transistors, where each of the ECUs includes a second circuit, the second circuit including a portion of the second transistors, where each of the at least four ECUs includes a first vertical bus, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where each of the at least four ECUs includes at least one processor and at least one memory array, where the second level is bonded to the first level, and the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.

Abstract: 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; second metal layer overlaying first metal layer; a second level including second transistors, first memory cells (each including at least one second transistor) and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells; third metal layer disposed above third level; fourth metal layer includes global power distribution grid, has a thickness at least twice the second metal layer, disposed above third metal layer; fourth level includes single-crystal silicon, atop f

Abstract: A 3D semiconductor device, the device including: a first level including first single crystal transistors; and a second level including second single crystal transistors, where the first level is overlaid by the second level, where a vertical distance from the first single crystal transistors to the second single crystal transistors is less than eight microns, where the second level includes a layer transferred and bonded level, where the bonded includes oxide to oxide bonds, where the first level includes a plurality of processors, and where the second level includes a plurality of memory cells.

Abstract: An adjustable brace for stabilizing a body part of a patient and a method of fabricating such a brace is provided. In some embodiments, the adjustable brace comprises a first 3D printed stabilizer having a first exterior surface, a first interior surface, and a first thickness; a second stabilizer comprising a second exterior surface, a second interior surface, and a second thickness; one or more attachment points; and one or more selective engagement structures, wherein the first 3D printed stabilizer selectively engages with the second 3D printed stabilizer at common peripheries of the first 3D printed stabilizer and second 3D printed stabilizer via the one or more selective engagement structures, respectively; and a position of the first 3D printed stabilizer is adjustable in relation to the second 3D printed stabilizer.

Abstract: A 3D semiconductor device including: a first level including a single crystal layer, a memory control circuit which includes a plurality of first transistors; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors which include a metal gate are disposed atop the third metal layer; third transistors disposed atop the second transistors; a fourth metal layer disposed atop the third transistors; and a memory array including word-lines, the memory array includes at least four memory mini arrays, each including at least four rows by at least four columns of memory cells, where each of the memory cells includes at least one of the second transistors or at least one of the third transistors, the memory control circuit includes at least one Look Up Table circuit (“LUT”).

Abstract: A 3D semiconductor device, the device including: a first level including first single crystal transistors; and a second level including second single crystal transistors, where the first level is overlaid by the second level, where the first level includes a transferred layer and a bonded layer, where the second level is bonded to the first level, where the bonded second level includes oxide to oxide bonds, where the bonded second level includes metal to metal bonds, where the first level includes memory periphery circuits, where the second level includes a plurality of memory cells, and where the first level includes at least one Look up Table (“LUT”) circuit.

Abstract: A semiconductor device including: a first level including first memory arrays, a plurality of first transistors, and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes second memory arrays; a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, where the second filled holes are aligned to the first filled holes with a more than 1 nm but less than 40 nm alignment error, and where the third level includes decoder circuits.

Abstract: A semiconductor device including: a first level including first memory arrays, a plurality of first transistors, and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes second memory arrays; a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, where the second filled holes are aligned to the first filled holes with a more than 1 nm but less than 40 nm alignment error, and where the third level includes decoder circuits.

Abstract: An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level with an oxide to oxide bond; a plurality of pixel control circuits; a plurality of memory circuits; and a third level disposed underneath the first level, where the third level includes a plurality of third transistors.

Abstract: A semiconductor device including: a first silicon layer including a first single crystal silicon layer; first transistors with a single crystal channel and overlaid by a first metal layer; overlaid by a second metal layer; overlaid by a third metal layer; a second level with second transistors and including a metal gate, and then disposed over the third metal layer; the second level is overlaid by a third level with third transistors; and then overlaid by a fourth metal layer; fourth overlaid by a fifth metal layer; parts of the second transistors are made with Atomic Layer Deposition (“ALD”); the fifth metal layer average thickness is greater than the third metal layer average thickness by at least 50%; at least one element within at least one of the second transistors has been processed independently of the third transistors.

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including at least one electromagnetic wave receiver, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the integrated circuits include at least one memory circuit, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

Abstract: 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; second metal layer overlaying first metal layer; a second level including second transistors, first memory cells (each including at least one second transistor) and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells; third metal layer disposed above third level; fourth metal layer includes global power distribution grid, has a thickness at least twice the second metal layer, disposed above third metal layer; fourth level includes single-crystal silicon, atop f

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.