Abstract: An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level, where the bonded includes an oxide to oxide bond; and a plurality of pixel control circuits, where each of the plurality of image sensors is directly connected to at least one of the plurality of pixel control circuits, and where the integrated device includes a plurality of memory circuits.

Abstract: An electrical passenger car, the electrical passenger car including: at least two electrically driven motors; motor control electronics, where the motor control electronics are connected to the at least two electrically driven motors; wheels, where the wheels are connected to the at least two electrically driven motors; and sensors, where the sensors are connected to at least the motor control electronics, where the wheels include a first wheel and a second wheel, where the second wheel has a radius at least 7% greater than a radius of the first wheel, where the motor control electronics control the at least two electrically driven motors to provide a greater torque to the first wheel than to the second wheel, and where the electrical passenger car is designed to operate efficiently on a paved road.

Abstract: A semiconductor device, the device including: a first level including a plurality of first memory arrays, where the first level includes a plurality of first transistors and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes a plurality of second memory arrays; a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, and where the third level includes a plurality of decoder circuits.

Abstract: A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming a first metal layer on top of first level; forming a second metal layer on top of the first metal layer; forming at least one second level above the second metal layer; performing a first lithography step on the second level; forming a third level on top of the second level; performing a second lithography step on the third level; perform processing steps to form first memory cells within the second level and second memory cells within the third level, where first memory cells include at least one second transistor, and the second memory cells include at least one third transistor; and deposit a gate electrode for the second and the third transistors simultaneously.

Abstract: In vat polymerization printer, light is projected from a digital light processing (DLP) light source towards an opening in a tank containing photo-curable liquid resin. A mask is used to filter the light from the DLP light source, the mask having pixels configurable to be individually transparent or opaque to portions of the light from the DLP light source. In a build area of the tank, the filtered light is used to cure the photo-curable liquid resin so as to form a layer of a partially formed object. The operation of the DLP light source is synchronized with the operation of the mask, such that light from the DLP light source with high intensity is transmitted through the transparent pixels of mask and light from DLP light source with low intensity is blocked by the opaque pixels of mask. The mask may enhance the resolution of DLP light source.

Abstract: A method for producing 3D semiconductor devices including: providing a first level including first transistors and a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one second level on top of or above the second metal layer; performing a lithography step on the second level; forming at least one third level on top of or above the second level; performing processing steps to form first memory cells within the second level and second memory cells within the third level, where the first memory cells include at least one second transistor, the second memory cells include at least one third transistor, first transistors control power delivery to some second transistors; and then forming at least four independent memory arrays which include some first memory cells and/or second memory cells.

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the integrated circuits include at least one memory circuit, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

Abstract: An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of semiconductor devices; a third level overlaying the second level, where the third level includes a plurality of image sensors, where the first level includes a plurality of landing pads, where the second level is bonded to the first level, where the bonded includes an oxide to oxide bond; and an isolation layer disposed between the second mono-crystal layer and the third level.

Abstract: Provided herein are ligament docking implants and methods for making and using the same. In at least one embodiment, the implants include at least one docking recess configured to receive a tissue structure such as a ligament and connect said tissue to the implant via suitable surgical techniques. In at least one embodiment, the docking recesses of the implant include a gyroid architecture that provides for improved mechanical performance and tissue integration. In various embodiments, the present methods of using the ligament docking implants include the use of sutures to connect tissue to the implant via the docking recess.

Abstract: A 3D memory device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the plurality of bit-line pillars are vertically oriented, where the channel is horizontally oriented, where each of the at least one memory transistor is directly connected to at least one of the plurality of bit-line pillars, where the plurality of memory cells include a partially or fully metalized source structure and/or a partially or fully metalized drain structure, where the metalized source includes two metal structures, and where the two metal structures include a tungsten structure.

Abstract: A method for producing 3D semiconductor devices including: providing a first level including first transistors and a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one second level on top of or above the second metal layer; performing a lithography step on the second level; forming at least one third level on top of or above the second level; performing processing steps to form first memory cells within the second level and second memory cells within the third level, where the first memory cells include at least one second transistor, the second memory cells include at least one third transistor, first transistors control power delivery to some second transistors; and then forming at least four independent memory arrays which include some first memory cells and/or second memory cells.

Abstract: A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors, the second level overlaying the first level; and at least four electronic circuit units (ECUs), where each of the ECUs include a first circuit, the first circuit including a portion of the first transistors, where each of the ECUs includes a second circuit, the second circuit including a portion of the second transistors, where each of the ECUs includes a first vertical bus, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where each of the ECUs includes at least one processor and at least one memory array, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.

Abstract: A system comprising: a user device, comprising: sensors configured to sense data related to a physical environment of the user device, displays; hardware processors; and a non-transitory machine-readable storage medium encoded with instructions executable by the hardware processors to: place a virtual object in a 3D scene displayed by the second user device, determine a pose of the user device with respect to the physical location in the physical environment of the user device, and generate an image of virtual content based on the pose of the user device with respect to the placed virtual object, wherein the image of the virtual content is projected by the one or more displays of the user device in a predetermined location relative to the physical location in the physical environment of the user device.

Abstract: The present disclosure generally discloses instruments and methods of using those instruments for performing various aspects of ankle replacement surgery. In one embodiment, an alignment assembly for adjusting a position of a guide tool relative to a patient is provided. The alignment assembly includes a proximal housing; a distal housing configured to be connected to the guide tool; and at least one linkage system configured to adjust a relative angle between at least two portions of the alignment assembly. A surgical guide wire is also disclosed. The surgical guide wire includes a distal tip having a tapered or trocar end configured for insertion into a bone; a distal region adjacent to the distal tip; a transition region adjacent to the distal region; and a proximal region adjacent to the transition region.

Abstract: A virtual reality network performer system includes a scene setup module, a recording module and a processing module. The scene setup module receives a scene setup instruction inputted by a performer in order to set a plurality of environmental parameters. The recording module receives a voice data, a body motion data and a face data of the performer. The processing module performs a voice changing for the voice data to generate a voice changing result, and analyzes the body motion data and the face data to generate a body motion and a face expression. Then, the processing module saves the environmental parameters, the voice changing result, the body motion and the face expression in a cloud storage module in order to form a cloud data.

Abstract: A semiconductor device, the device including: a first level including a plurality of first memory arrays, where the first level includes a plurality of first transistors and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes a plurality of second memory arrays; a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, and where the third level includes a plurality of decoder circuits.

Abstract: A surgical guide assembly is disclosed herein that includes instruments configured to aid in the alignment of surgical instruments. In one aspect, a first and second instrument are provided that are configured to be connected to each other via interfaces and each define bone contact interface. The bone contact interfaces are configured to engage with the tibia and talus, in one embodiment.

Abstract: A semiconductor device including: a plurality of transistors, where at least one of the transistors includes a first single crystal source, channel, and drain, where at least one of the transistors includes a second single crystal source, channel, and drain, where the second single crystal source, channel, and drain is disposed above the first single crystal source, channel, and drain, where at least one of the transistors includes a third single crystal source, channel, and drain, where the third single crystal source, channel, and drain is disposed above the second single crystal source, channel, and drain, where at least one of the transistors includes a fourth single crystal source, channel, and drain, where the fourth single crystal source, channel, and drain is disposed above the third single crystal source, channel, and drain, and where the fourth drain is aligned to the first drain with less than 40 nm misalignment.

Abstract: A semiconductor device, the device including: a first silicon layer including a first single crystal silicon layer; a plurality of first transistors each including a single crystal channel; a first metal layer disposed over the plurality of first transistors; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer; a via disposed through the second level, where at least one of the plurality of second transistors includes a metal gate, where an average thickness of the fifth metal layer is greater than an average thickness of the third metal layer by at least 50%; and at least one Electrostatic discharge (“ESD”) structure.