Abstract: An augmented reality collaboration system comprises a first system configured to display virtual content, comprising: a structure comprising a plurality of radiation emitters arranged in a predetermined pattern, and a user device comprising: one or more sensors configured to sense outputs of the plurality of radiation emitters, and one or more displays; one or more hardware processors; and a non-transitory machine-readable storage medium encoded with instructions executable by the one or more hardware processors to, for the user device: determine a pose of the user device with respect to the structure based on the sensed outputs of the plurality of radiation emitters, and generate an image of virtual content based on the pose of the user device with respect to the structure, wherein the image of the virtual content is projected by the one or more displays of the user device in a predetermined location relative to the structure.

Abstract: A semiconductor device, the device including: a first silicon layer including a first single crystal silicon layer; a plurality of first transistors each including a single crystal channel; a first metal layer disposed over the plurality of first transistors; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer; a via disposed through the second level, where at least one of the plurality of second transistors includes a metal gate, where an average thickness of the fifth metal layer is greater than an average thickness of the third metal layer by at least 50%; and at least one Electrostatic discharge (“ESD”) structure.

Abstract: A semiconductor device, the device including: a first substrate; a first metal layer disposed over the first substrate; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors each include single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 200 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm, where the fourth metal layer provides a global power distribution, and where the device includes at least one power supply circuit.

Abstract: A 3D memory device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of memory-line pillars, where each memory-line pillar of the plurality of memory-line pillars is directly connected to a plurality of the source or the drain, where the plurality of memory-line pillars are vertically oriented, where the channel is horizontally-oriented and a plurality are connected to a body pillar, where the body pillar is at least temporary connected to a negative bias, the at least one memory transistor is self-aligned to an overlaying another memory transistor, both being processed following a same lithography step; a control level including a memory controller circuit and is hybrid bonded to the first structure.

Abstract: A 3D device, the device including: at least a first level including logic circuits; and at least a second level bonded to the first level, where the second level includes a plurality of transistors, where the device include connectivity structures, where the connectivity structures include at least one of the following: a. differential signaling, or b. radio frequency transmission lines, or c. Surface Waves Interconnect (SWI) lines, and where the bonded includes oxide to oxide bond regions and metal to metal bond regions.

Abstract: A 3D memory device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of memory-line pillars, where each memory-line pillar of the plurality of memory-line pillars is directly connected to a plurality of the source or the drain, where the plurality of memory-line pillars are vertically oriented, where the channel is horizontally-oriented and a plurality are connected to a body pillar, where the body pillar is at least temporary connected to a negative bias, the at least one memory transistor is self-aligned to an overlaying another memory transistor, both being processed following a same lithography step; a control level including a memory controller circuit and is hybrid bonded to the first structure.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.

Abstract: A 3D semiconductor device including: a first level including a plurality of first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the plurality of first single-crystal transistors; a first metal layer disposed atop the plurality of first single-crystal transistors; a second metal layer disposed atop the first metal layer; a second level disposed atop the second metal layer, the second level including a plurality of second transistors; a third level including a plurality of third transistors, where the third level is disposed above the second level; a third metal layer disposed above the third level; and a fourth metal layer disposed above the third metal layer, where the plurality of second transistors are aligned to the plurality of first single crystal transistors with less than 140 nm alignment error, the second level includes first memory cells, the third level includes second memory cells.

Abstract: A method and system for providing the ability to deform and adapt a 3D model and associated 3D object to comply with a set of extrinsic and intrinsic constraints to guarantee function and fit with respect to a 3D target object. The method includes simplifying the 3D object with a topological simplification, identifying a number of constraint zones according to defined characteristics such as external rigid and non-rigid zones and internal rigid and non-rigid zones, and modifying the 3D model with respect to the constraint zones.

Abstract: A process to cure and/or modify the surface of a three dimensional (3D) printed part comprising the steps of immersing a three dimensional (3D) printed part, containing reactive moieties, into a liquid bath at an elevated temperature to effect polymerization of the reactive moieties of the 3D printed part to provide a cured 3D printed part is described. The liquid bath can further contain reactive molecules that can react with the surface of the 3D printed part to provide a coating which alters the surface characteristics of the 3D printed part.

Abstract: An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level with an oxide to oxide bond; a plurality of pixel control circuits; a plurality of memory circuits; and a third level disposed underneath the first level, where the third level includes a plurality of third transistors.

Abstract: A clavicle protective device may include a contoured member configured to cover at least a portion of the clavicle. The contoured member may have an inner surface configured to face the at least a portion of the clavicle and an outer surface configured to face away from the at least a portion of the clavicle. The contoured member may include a first contact portion, a second contact portion, and a bridge portion positioned between the first contact portion and the second contact portion. The first contact portion may be configured to contact the subject's body above the clavicle. The second contact portion may be configured to contact the subject's body below the clavicle. The bridge portion may be configured to be spaced apart from the subject's body when the first contact portion and the second contact portion contact the subject's body.

Abstract: A 3D semiconductor device, the device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each transistor of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the transistors of the plurality of transistors, and where the second level is overlaid by a first isolation layer; and a connective path from the plurality of transistors to the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where at least one of the via includes a contact to at least one of the transistors.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where at least one of the second transistors includes a raised source or raised drain transistor structure, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.

Abstract: An imaging system includes a transmissive diffraction mask (TDM), a pixel array, and a processor. The TDM includes a first and a second diffraction grating configured to diffract light received from a scene to generate first diffracted light encoding information about an angle of incidence (AOI) of the received light and second diffracted light encoding information about the AOI and a state of polarization (SOP) of the received light, respectively. The pixel array includes a first and a second set of pixels configured to detect the first and second diffracted light and generate therefrom a corresponding first and second set of pixel responses, respectively. The processor is configured to determine, from the first set of pixel responses, AOI data conveying the AOI of the received light, and determine, from the second set of pixel responses and the AOI data, polarization data conveying the SOP of the received light.

Abstract: Methods and systems for forming objects through photo-curing of a liquid resin in a tank by selective exposure (through a mask) to radiation, in which during printing operations the liquid resin in the tank is displaced relative to the build area along an axis orthogonal to that along which the object is extracted from the liquid resin in the tank. A volume of the photo-curing liquid resin may be cycled through a cooling arrangement by being extracted from the tank, cooled, and then reintroduced into the tank as printing of the object is taking place. The mask is preferably one in which charged colorant particles are dispersed in an optically transparent fluid within a plurality of bi-state cells.

Abstract: A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; a second metal layer overlaying first metal layer; a second level including second transistors, first memory cells (each including at least one second transistor) and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells; third metal layer disposed above third level; fourth metal layer includes a global power distribution grid, has a thickness at least twice the second metal layer, and is disposed above third metal layer.