Abstract: An accumulation mode transistor has an impurity concentration of a semiconductor layer in a channel region at a value higher than 2×1017 cm?3 to achieve a large gate voltage swing.

Abstract: A transistor capable of adjusting a threshold value is obtained by adjusting an impurity concentration of a silicon substrate supporting an SOI layer and by controlling a thickness of a buried insulating layer formed on a surface of the silicon substrate in contact with the SOI layer.

Abstract: A multilayer wiring board 100 comprises a first wiring region 101 where wirings 103a and insulating layers 104a and 104b are alternately laminated, and a second wiring region 102 where a thickness H2 of an insulating layer 104 is twice or more a thickness H1 of the insulating layer in the first wiring region 101 and a width W2 of a wiring 103b is twice or more a width W1 of the wiring in the first wiring region 101. The first wiring region 101 and the second wiring region 102 are integrally formed on the same board.

Abstract: With respect to a vacuum tube having a reduced pressure vessel containing an electric discharge gas sealed therein, problems such as the lowering of discharge efficiency owing to an organic material, moisture or oxygen remaining in the reduced pressure vessel have taken place conventionally. It has been now found that the selection of the number of water molecules, the number of molecules of an organic gas and the number of oxygen molecules remaining in the reduced pressure vessel, in a relation with the number of molecules of a gas contributing the electric discharge allows the reduction of the adverse effect by the above-mentioned remaining gas. Specifically, the selection of the number of molecules of the above electric discharge gas being about ten times that of the above-mentioned remaining gas or more can reduce the adverse effect by the above-mentioned remaining gas.

Abstract: A semiconductor device manufacturing method which achieves a contact of a low resistivity is provided. In a state where a first metal layer in contact with a semiconductor is covered with a second metal layer for preventing oxidation, only the first metal layer is silicided to form a silicide layer with no oxygen mixed therein. As a material of the first metal layer, a metal having a work function difference of a predetermined value from the semiconductor is used. As a material of the second metal layer, a metal which does not react with the first metal layer at an annealing temperature is used.

Abstract: With respect to a vacuum tube having a reduced pressure vessel containing an electric discharge gas sealed therein, problems such as the lowering of discharge efficiency owing to an organic material, moisture or oxygen remaining in the reduced pressure vessel have taken place conventionally. It has been now found that the selection of the number of water molecules, the number of molecules of an organic gas and the number of oxygen molecules remaining in the reduced pressure vessel, in a relation with the number of molecules of a gas contributing the electric discharge allows the reduction of the adverse effect by the above-mentioned remaining gas. Specifically, the selection of the number of molecules of the above electric discharge gas being about ten times that of the above-mentioned remaining gas or more can reduce the adverse effect by the above-mentioned remaining gas.

Abstract: In a semiconductor device, the degree of flatness of 0.3 nm or less in terms of a peak-to-valley (P-V) value is realized by rinsing a silicon surface with hydrogen-added ultrapure water in a light-screened state and in a nitrogen atmosphere and a contact resistance of 10?11 ?cm2 or less is realized by setting a work function difference of 0.2 eV or less between an electrode and the silicon. Thus, the semiconductor device can operate on a frequency of 10 GHz or higher.

Abstract: A MIS transistor, formed on a semiconductor substrate, assumed to comprise a semiconductor substrate (702, 910) comprising a projecting part (704, 910B) with at least two different crystal planes on the surface on a principal plane, a gate insulator (708, 920B) for covering at least a part of each of said at least two different crystal planes constituting the surface of the projecting part, a gate electrode (706, 930B), comprised on each of said at least two different crystal planes constituting the surface of the projecting part, which sandwiches the gate insulator with the said at least two different planes, and a single conductivity type diffusion region (710a, 710b, 910c, 910d) formed in the projecting part facing each of said at least two different crystal planes and individually formed on both sides of the gate electrode. Such a configuration allows control over increase in the element area and increase of channel width.

Abstract: Surface treatment is performed with a liquid, while shielding a semiconductor surface from light. When the method is employed for surface treatment in wet processes such as cleaning, etching and development of the semiconductor surface, increase of surface microroughness can be reduced. Thus, electrical characteristics and yield of the semiconductor device are improved.

Abstract: As a substrate for a semiconductor device, a metal substrate is used, and the metal substrate is composed of a metal base body made of a first metal and a connecting metal layer made of a second metal for covering the metal base body. The substrate has a structure wherein a diffusion preventing layer for preventing diffusion of the first metal is provided on the connecting metal layer.

Abstract: This invention provides an interlayer insulating film for a semiconductor device, which has low permittivity, is free from the evolution of gas such as CFx and SiF4 and is stable, and a wiring structure comprising the same. In an interlayer insulating film comprising an insulating film provided on a substrate layer, the interlayer insulating film has an effective permittivity of not more than 3. The wiring structure comprises an interlayer insulating film, a contact hole provided in the interlayer insulating film, and a metal filled into the contact hole. The insulating film comprises a first fluorocarbon film provided on the substrate layer and a second fluorocarbon film provided on the first fluorocarbon film.

Abstract: In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.

Abstract: An accumulation mode transistor has an impurity concentration of a semiconductor layer in a channel region at a value higher than 2×1017 cm?3 to achieve a large gate voltage swing.

Abstract: A gas or an insulating material having a relative dielectric constant of not more than 2.5 on average is interposed between a first wiring layer and a second wiring layer included in a multilayer wiring structure. Between a wiring of the first wiring layer and a wiring of the second wiring layer, a conductive connector is arranged. Between a predetermined wiring of the first wiring layer and a predetermined wiring of the second wiring layer, an insulating heat conductor having a relative dielectric constant of not more than 5 is arranged.

Abstract: The application of oxynitriding treatment to electronic appliances involve the problem that N2 ions are formed to thereby damage any oxynitride film. It is intended to provide a method of plasma treatment capable of realizing high-quality oxynitriding and to provide a process for producing an electronic appliance in which use is made of the method of plasma treatment. There is provided a method of plasma treatment, comprising generating plasma with a gas for plasma excitation and introducing a treating gas in the plasma to thereby treat a treatment subject, wherein the treating gas contains nitrous oxide gas, this nitrous oxide gas introduced in a plasma of <2.24 eV electron temperature, so that the generation of ions tending to damage any insulating film is reduced to thereby realize high-quality oxynitriding. Further, there is provided a process for producing an electronic appliance in which use is made of the method of plasma treatment.

Abstract: A semiconductor device according to this invention is provided with a MOS transistor of at least one type, wherein the MOS transistor has a semiconductor layer (SOI layer) provided on an SOI substrate and a gate electrode provided on the SOI layer and is normally off by setting the thickness of the SOI layer so that the thickness of a depletion layer caused by a work function difference between the gate electrode and the SOI layer becomes greater than that of the SOI layer.

Abstract: A system for processing a substrate uniformly by increasing the number of gas discharge holes being arranged per unit area of a shower plate as receding from the center of the shower plate or increasing the radii of the gas discharge holes as receding from the center of the shower plate thereby making the plasma excitation gas flow uniform.

Abstract: For equalizing the rising and falling operating speeds in a CMOS circuit, it is necessary to make the areas of a p-type MOS transistor and an n-type MOS transistor different from each other due to a difference in carrier mobility therebetween. This area unbalance prevents an improvement in integration degree of semiconductor devices. The NMOS transistor and the PMOS transistor each have a three-dimensional structure with a channel region on both the (100) plane and the (110) plane so that the areas of the channel regions and gate insulating films of both transistors are equal to each other. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other. Further, the integration degree on a substrate can be improved twice as much as that in the conventional technique.

Abstract: A film with small hysteresis and high voltage resistance is obtained by reducing the carbon content in a gate insulating film on a SiC substrate. Specifically, the carbon content in the gate insulating film is set to 1×1020 atoms/cm3 or less. For this, using a plasma processing apparatus, a silicon oxide film is formed on the SiC substrate and then the formed silicon oxide film is reformed by exposure to radicals containing nitrogen atoms. Thus, the gate insulating film excellent in electrical properties is obtained.

Abstract: In order to obtain substantially the same operating speed of a p-type MOS transistor and an n-type MOS transistor forming a CMOS circuit, the n-type MOS transistor has a three-dimensional structure having a channel region on both the (100) plane and the (110) plane and the p-type MOS transistor has a planar structure having a channel region only on the (110) plane. Further, both the transistors are substantially equal to each other in the areas of the channel regions and gate insulating films. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other.