Abstract: A testing system includes a testing apparatus and a crack noise monitoring device. The testing apparatus includes a testing stage and an element pickup module for pressing a semiconductor element on the testing stage. The crack noise monitoring device includes a database unit, a sound conduction set, a voiceprint generation unit and a processing unit. The database unit has a first voiceprint pattern. The sound conduction set is connected to the voiceprint generation unit and the testing apparatus for transmitting a sound wave from the semiconductor element to the voiceprint generation unit. The voiceprint generation unit receives and converts the sound wave into a second voiceprint pattern. The processing unit is electrically connected to the voiceprint generating unit and the database unit for determining whether the first voiceprint pattern is identical to the second voiceprint pattern.

Abstract: A semiconductor device with an interface includes a master device and a plurality of slave devices. The master device includes a master interface. The slave devices are stacked on the master device one after one as a three-dimension (3D) stack. Each of the slave devices includes a slave interface and a managing circuit, the master interface and the slave interfaces form the interface for passing signals in communication between the master device and the slave devices. The managing circuit of a current one of the slave devices drives a next one of the slave devices. An operation command received at the current one of the slave devices is just passed to the next one of the slave devices through the interface. A response from the current one of the slave devices is passed back to the master device through the interface.

Abstract: An interface for a semiconductor device is provided. The semiconductor device has a master device and multiple slave devices as stacked up with electric connection. The interface includes a master interface, implemented in the master device and including a master interface circuit with a master bond pattern. Further, a slave interface is implemented in each slave device and includes a slave interface circuit with a slave bond pattern to correspondingly connect to the master bond pattern. A clock route is to transmit a clock signal through the master interface and the slave interface. The master device transmits a command and a selecting slave identification through the master interface to all the slave interfaces. One of the slave devices corresponding to the selecting slave identification executes the command and responds a result back to the master device through the slave interfaces and the master interface.

Abstract: A data protection system and a data protection method for handling an errored command are provided. The data protection system includes a master device and a slave device. The master device is configured to send command. The slave device is coupled to the master device. The save device is configured to receive the command from the master device. The master device includes a master interface. The slave device includes a slave interface. The master interface and the slave interface are electrically connected via one or plurality of bonds and/or TSVs and configured for interfacing between the master device and the slave device. The errored command represents the command having a parity or other error. The slave device is further configured to receive the errored command and to respond the errored command according to read or write operation.

Abstract: A pogo pin-free testing device for IC chip test includes a load board, a ceramic interposer disposed on the load board, and copper core balls. The ceramic interposer has first and second surfaces and connecting points, and the second surface of the ceramic interposer faces the load board. Each connecting point has through holes penetrating the first and second surfaces, and an inner sidewall surface thereof has a metallization layer. The metallization layer is extended to a portion of the first surface and a portion of the second surface. In each of the connecting points, an area of an extending portion of the metallization layer extended to the second surface is less than an area of an extending portion of the metallization layer extended to the first surface. The copper core balls are disposed between the load board and the through holes of each connecting point of the ceramic interposer.

Abstract: A manufacturing method of a semiconductor packaging device is provided, and the manufacturing method includes steps as follows. A working chip is soldered on one surface of a wiring board so that an working circuit inbuilt inside a chip body of the working chip is electrically connected to the wiring board. A silicon thermal conductivity element is soldered on one surface of a heat-dissipating metal lid. The heat-dissipating metal lid is fixedly covered on the wiring board such that the silicon thermal conductivity element is sandwiched between the chip body and the heat-dissipating metal lid, and the silicon thermal conductivity element is electrically isolated from the working circuit of the chip body and the wiring board.

Abstract: An interposer, including a redistribution layer structure, first conductive terminals, and second conductive terminals, is provided. The first conductive terminals are disposed on a first surface and are electrically connected to the second conductive terminals. An orthographic projection area of the first conductive terminals on the redistribution layer structure is inside a circuit range outline. There is a first pitch between the adjacent first conductive terminals. The second conductive terminals are disposed on a second surface. An orthographic projection area of a first part of the second conductive terminals on the redistribution layer structure is inside the circuit range outline. An orthographic projection area of a second part of the second conductive terminals on the redistribution layer structure is outside the circuit range outline. There is a second pitch between the adjacent second conductive terminals. The second pitch is greater than the first pitch. A semiconductor package is also provided.

Abstract: An apparatus for adjusting skew of circuit signal and an adjusting method thereof are provided. The adjusting method includes: providing a controller for executing: based on each of a plurality of clock signals, dividing a circuit to generate a plurality of circuit partitions according to a netlist of the circuit; grouping the circuit partitions to respectively generate a plurality of circuit groups; identifying adjacent states of layout areas of the circuit groups; and, adjusting a skew value of each of the circuit groups according to the adjacent states.

Abstract: A testing socket includes a metal block, an assembly block, an analog ground probe pin and a digital ground probe pin. The metal block is formed with a concave portion and used to connect to an independent main ground. The assembly block is electrically isolated from the metal block, and detachably embedded in the recess, so that the metal block and the assembly block are assembled together to be a probe holder. The digital grounding probe is inserted in the metal block, electrically connected to the independent main ground through the metal block. The digital ground probe pin can be electrically connected to a device to be tested (DUT) and the independent main ground. The analog ground probe pin is inserted in the assembly block, and electrically connected to the DUT and another independent main ground.

Abstract: A routing structure between dies is provided, including a trace layer, disposed on a substrate, wherein a plurality of routing paths is embedded in the trace layer. In addition, a first die and a second die are disposed on the trace layer and connected by the routing paths. A spacing gap between the first die and the second die is along a first direction and interfacing edges of the first die and the second die are extending along a second direction perpendicular to the first direction. Each of the routing paths includes a first straight portion in parallel to connect to the interfacing edges. The first straight portion has a slant angle with respect to the first direction other than 0° and 90°.

Abstract: A communication system and an operation method thereof are provided. The transmitting device transmits the current data unit and the transmitted data verification information to the receiving device through the communication interface, and records the current data unit in an FIFO buffer. The receiving device counts the received data identification value by itself based on the current data unit received from the communication interface. The receiving device uses the received data identification value and the transmitted data verification information to check whether the current data unit received from the communication interface has errors. When the current data unit is in error, the receiving device returns an error flag to the transmitting device so that the transmitting device suspends the transmission of the new data unit, and transmits the buffered data unit recorded in the FIFO buffer to the receiving device through the communication interface.

Abstract: A circuit board device includes a multilayer structure, a main ground area and a circuit module. The multilayer structure includes a plurality of plates. The main ground area is arranged in the multilayer structure. The circuit module includes a differential signal circuit and a surrounding circuit module. The differential signal circuit is located in the multilayer structure, and includes a positive signal pad and a negative signal pad. The positive signal pad is located on a configuration surface of one of the plates. The negative signal pad is located on the disposition surface, and is separated from the positive signal pad. The surrounding circuit module is located on the disposition surface, and electrically connected to the main ground area. The surrounding circuit module surrounds the positive signal pad and the negative signal pad in an enclosing way, and is physically separated from the differential signal circuit.

Abstract: An electrostatic discharge (ESD) protection device includes a first clamping circuit, a second clamping circuit, and a diode circuit. The first clamping circuit is coupled between a first power rail and a second power rail. The second clamping circuit is coupled between a third power rail and the second power rail. The diode circuit is configured to steer an ESD current from an input/output pad to at least one of the first clamping circuit or the third power rail. The first power rail receives a first voltage, the second power rail receives a second voltage, the third power rail receives a third voltage, the third voltage is higher than the first voltage, and the first voltage is higher than the second voltage.

Abstract: An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit and a controlling circuit. The ADC circuits are configured to generate first quantized outputs according to clock signals. The calibration circuit is configured to perform at least one error operation according to the first quantized outputs to generate second quantized outputs, and is configured to analyze time difference information of the clock signals according to the second quantized outputs to generate adjustment signals. The controlling circuit is configured to analyze the first quantized outputs to generate at least one control signal to the calibration circuit, wherein the at least one control signal is configured to control the calibration circuit to selectively perform the at least one error operation and selectively analyze the time difference information of the clock signals.

Abstract: A communication interface structure for connection between dies is provided, including a memory die, processing dies and interconnection routings. The memory die includes a first interface edge, wherein the first interface edge is split into a plurality of interface groups. Each of the processing dies includes a second interface edge. Interconnection routings respectively connect the second interface edges of the processing dies to the interface groups of the memory die.

Abstract: An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit and a skew adjusting circuit. The ADC circuits convert an input signal according to clock signals, to generate first quantized outputs. The calibration circuit calibrates the first quantized outputs to generate second quantized outputs. The skew adjusting circuit includes an estimating circuit and a feedback circuit. The estimating circuit analyzes the second quantized outputs to generate detection signals, wherein the detection signals are related to time difference information of the clock signals. The skew adjusting circuit outputs the detection signals as adjustment signals, wherein the adjustment signals are configured to reduce a clock skew of the ADC circuits. The feedback circuit analyzes the detection signals generated by the estimating circuit, to generate a feedback signal to the estimating circuit, wherein the estimating circuit is configured to adjust the detection signals according to the feedback signal.

Abstract: A circuit is provided for providing a sampling clock to de-serializers in a communication physical layer. The circuit includes a slave delay lock loop (DLL), to receive an input clock and provide the sampling clock to the de-serializers. Further, a master DLL is included for receiving the input clock and outputting a control signal to the slave DLL to adjust a delay amount of the sampling clock of the slave DLL. The master DLL replicates a circuit of the slave DLL with a loop detection and determines the control signal for output.

Abstract: A semiconductor packaging device includes a wiring board, a working chip, a heat-dissipating metal lid and a silicon thermal conductivity element. The working chip is mounted on the wiring board, and in-built with an working circuit therein. The silicon thermal conductivity element is thermally coupled to the working chip and the heat-dissipating metal lid, and is electrically isolated from the working circuit and the wiring board.

Abstract: A temperature sensing device and a temperature sensing method are provided. The temperature sensing device includes a sensor and an analog-to-digital converter. The sensor generates a first sensing result corresponding to an ambient temperature based on a first condition and generates a second sensing result corresponding to the ambient temperature based on a second condition. The second sensing result is different from the first sensing result. The analog-to-digital divides the first sensing result and the second sensing result to obtain a quotient value and generates an output digital code value corresponding to the ambient temperature according to the quotient value.

Abstract: A routing structure between dies is provided, including a trace layer, disposed on a substrate, wherein a plurality of routing paths is embedded in the trace layer. In addition, a first die and a second die are disposed on the trace layer and connected by the routing paths. A spacing gap between the first die and the second die is along a first direction and interfacing edges of the first die and the second die are extending along a second direction perpendicular to the first direction. Each of the routing paths includes a first straight portion in parallel to connect to the interfacing edges. The first straight portion has a slant angle with respect to the first direction other than 0° and 90°.