Abstract: A circuit structure including a first signal line and a second signal line is provided. The first signal line includes a first line segment, a first ball grid array pad, and a first through hole disposed between the first line segment and the first ball grid array pad. The second signal line includes a second line segment, a second ball grid array pad, and a second through hole disposed between the second line segment and the second ball grid array pad. In a plan view, a line connecting the center of the first ball grid array pad and the center of the second ball grid array pad has a first distance, a line connecting the center of the first through hole and the center of the second through hole has a second distance, and the first distance is less than the second distance. A chip package is also provided.

Abstract: A comparator circuitry includes an input pair circuit, a load circuit, and a compensation circuit. The input pair circuit is configured to compare a first input signal with a second input signal, in order to control a first bias current. The load circuit is coupled to the input pair circuit, and is configured to output an output signal having a first level from a first output terminal of the load circuit in response to the first bias current. The compensation circuit is coupled to the input pair circuit and the load circuit, and is configured to drain a compensation current from the first output terminal to a voltage source during the load circuit generates the output signal having a first level, in which the voltage source is configured to provide a voltage having a second level.

Abstract: A timing model building method, for building a timing model corresponding to a gate-level netlist of a block, includes the following operations: utilizing a processor to generate an interface net of the gate-level netlist, where if the gate-level netlist comprises an unconstrained clock tree and boundary timing constraint information of the gate-level netlist does not comprise a timing constraint of the unconstrained clock tree, the interface net comprises none of cells of the gate-level netlist driven by the unconstrained clock tree; utilizing the processor to generate an identified internal net of the gate-level netlist, where the identified internal net is cross-coupled to the interface net; and utilizing the processor to generate the timing model according to the interface net and the identified internal net.

Abstract: A voltage mode signal transmitter includes a front-end signal processor and a signal transformer. The front-end signal processor receives a first and second data signal, and delays and inverts the data signals to generate a third and fourth data signal. The front-end signal processor selects two of the first data signal to the fourth data signal to generate a plurality of signal pairs according to a first control signal. The signal transformer selects one data signal of each of the signal pairs to generate input voltages according to a second control signal, and generates an output voltage according to the input voltages. A working frequency of the first control signal is lower than a working frequency of the second control signal.

Abstract: An integrated circuit package element provided includes a chip element and a package module coupled to the chip element. The chip element includes two driving units that are electrically connected to each other. The package module includes a grounding area, two individual power distributed networks and a grounded shielding structure which is completely disposed between the individual power distributed networks, electrically connected to the chip element, and configured to block power noise coupling between the first electric power distribution network and the second electric power distribution network. The grounding area is electrically connected to the individual electric power distribution networks and the grounded shielding structure.

Abstract: A circuit structure including a first signal line and a second signal line is provided. The first signal line includes a first line segment, a first ball grid array pad, and a first through hole disposed between the first line segment and the first ball grid array pad. The second signal line includes a second line segment, a second ball grid array pad, and a second through hole disposed between the second line segment and the second ball grid array pad. In a plan view, a line connecting the center of the first ball grid array pad and the center of the second ball grid array pad has a first distance, a line connecting the center of the first through hole and the center of the second through hole has a second distance, and the first distance is less than the second distance. A chip package is also provided.

Abstract: An analog to digital converter (ADC) device includes ADC circuitries, a calibration circuitry, and a skew adjustment circuitry. The ADC circuitries are configured to convert an input signal according to interleaved clock signals, in order to generate first quantization outputs. The calibration circuitry is configured to perform at least one calibration operation according to the first quantization outputs, in order to generate second quantization outputs. The skew adjustment circuitry is configured to determine maximum value signals, to which the second quantization outputs respectively correspond during a predetermined interval, and to average the maximum value signals to generate a reference signal, and to compare the reference signal with each of the maximum value signals to generate adjustment signals, in order to reduce a clock skew of the ADC circuitries.

Abstract: A glitch measurement device is coupled to a circuit under-test and includes a counter circuitry and a detector circuitry. The counter circuitry is coupled to the circuit under-test, and is configured to perform a first counting operation according to an input signal transmitted to the circuit under-test to generate a first count signal, and to perform a second counting operation according to an output signal outputted from the circuit under-test to generate a second count signal. The detector circuitry is coupled to the circuit under-test and the counter circuitry, and is configured to receive the first count signal and the second count signal according to the input signal, and to generate a glitch indication signal according to the first count signal and the second count signal.

Abstract: A driver device includes a T-coil circuit and driver circuitries. The driver circuitries are averagely configured as a first driver set and a second driver set. The driver circuitries of the first driver set amplify one of a first data signal and a second data signal according to first portion of bits of an equalization signal, to generate a first output signal and to transmit the same to a first node of the T-coil circuit. The driver circuitries of the second driver set amplify one of the first data signal and the second data signal according to second portion of bits of the equalization signal, to generate a second output signal and to transmit the same to a second node of the T-coil circuit. The T-coil circuit further combines the first and second output signals as a third data signal, and transmits the third data signal to a channel.

Abstract: An eye diagram measurement device includes a first mapping circuitry, a count circuitry, a second mapping circuitry and a memory circuitry. The first mapping circuitry maps one of plurality of internal signals of an electronic device to a first data signal having a predetermined number of bits. The counter circuitry performs a counting operation according to the first data signal and a plurality of signal values associated with the predetermined number of bits, to generate a plurality of count signals. The second mapping circuitry maps the count signals respectively to a plurality of eye diagram measurement signals corresponding to a present phase. The memory circuitry stores the eye diagram measurement signals in order to provide the eye diagram measurement signals to an external system for generating an eye diagram measurement result of the electronic device.

Abstract: A conductive transmission line structure includes a first conductive transmission line and a second conductive transmission line. A first segment and a second segment of the first conductive transmission line are respectively disposed adjacent to a third segment and a fourth segment of the second conductive transmission line. Line widths of the first segment and the third segment are respectively smaller than line widths of the second segment and the fourth segment. A spacing between the first segment and the third segment is smaller than a spacing between the second segment and the fourth segment. The first segment and the third segment provide a first impedance, and the second segment and the fourth segment provide a second impedance. The first impedance is smaller than the second impedance. The first and the third signal transmission nodes receive a differential signal pair.

Abstract: A calibration method applicable for a SAR ADC comprising a capacitor array, comprises the following operations: Inputting an input signal to the SAR ADC, wherein the SAR ADC is configured to generate an output signal according to the input signal, and the output signal comprises multiple selected digital codes; calculating average code densities for multiple digital code groups, respectively, wherein the multiple digital code groups are determined by dividing the multiple selected digital codes, and each of the multiple digital code groups comprises one or more selected digital codes of the multiple selected digital codes; calibrating capacitance of a first under-correction capacitor element of the capacitor array according to the first comparison result.

Abstract: A signal transmission device includes a transceiver circuitry and a control circuitry. The transceiver circuitry is configured to receive first device data from an external device through a channel. The control circuitry is configured to calculate a least one system parameter of the transceiver circuitry based on the first device data, second device data associated with the transceiver circuitry, and at least one requirement of a predetermined communication protocol, in order to link with the external device.

Abstract: A digital-to-analog conversion device and a compensation circuit are provided. A digital-to-analog conversion device includes an R2R digital-to-analog converter and a compensation circuit. The R2R digital-to-analog converter is configured to receive a digital code with a plurality of bits and receive a reference voltage, and convert the digital code into an analog output signal according to the reference voltage. The compensation circuit is configured to receive the digital code, decode the digital code to generate a compensation code with a plurality of bits, and compensate the current value of the reference current according to the compensation code to generate a compensated reference current. The compensated reference current has a constant current value corresponding to different digital codes to make the reference voltage constant.

Abstract: A model-building method comprises following operations: reading a top netlist and a block model, wherein the top netlist comprises a first input node, a first output node and a multivibrator, the block model comprises a input node and a output node; obtaining a first subnetlist from the top netlist, wherein the first subnetlist comprises a component coupled between the input node and the first input node or the multivibrator; obtaining a second subnetlist from the top netlist, wherein the second subnetlist comprises a component coupled between the output node and the first output node or the multivibrator; obtaining a third subnetlist from the top netlist, wherein the third subnetlist comprises a component coupled between a clock input node of the multivibrator and a top clock input node of the top netlist; generating a top ILM according to the first to the third subnetlist.

Abstract: A conductive transmission line structure includes a first conductive transmission line and a second conductive transmission line. A first segment and a second segment of the first conductive transmission line are respectively disposed adjacent to a third segment and a fourth segment of the second conductive transmission line. Line widths of the first segment and the third segment are respectively smaller than line widths of the second segment and the fourth segment. A spacing between the first segment and the third segment is smaller than a spacing between the second segment and the fourth segment. The first segment and the third segment provide a first impedance, and the second segment and the fourth segment provide a second impedance. The first impedance is smaller than the second impedance. The first and the third signal transmission nodes receive a differential signal pair.

Abstract: A testing system for semiconductor package components includes a testing circuit board, a test socket, at least one probe pin and a thermal barrier layer element. The testing circuit board has at least one electrical contact. The test socket is used to receive a DUT. The probe pin is located on the test socket for contacting with the DUT. The thermal barrier layer element is located between the testing circuit board and the test socket, electrically connected to the probe pin and the electrical contact, and thermally isolated the electrical contact from the probe pin.

Abstract: An amplifier circuitry includes a current source circuit, a voltage regulator circuit, and an amplifier. The current source circuit generates a first bias current. The voltage regulator circuit regulates a reference voltage to generate a supply voltage. The voltage regulator circuit includes a first and a second compensation resistors, the first and the second compensation resistors are configured to generate the reference voltage according to a reference a second bias currents, and a first ratio is present between the first and the second biasing currents. The amplifier includes first load resistors which are configured to generate a first common-mode output signal based on the supply voltage and the first bias current. The second ratio is present between the second compensation resistor and one of the first load resistors, and the first and the second ratios are arranged to compensate the first common-mode output signal.

Abstract: A drying apparatus includes an oven body, a magnetic field generating device, a chamber pressure controlling device and a baking device. The oven body is provided with a chamber which is air-hermetic for receiving a semiconductor package element. The chamber pressure controlling device reduces a chamber pressure of the chamber. The magnetic field generating device polarizes liquid on the semiconductor package element in the chamber. The baking device evaporates the liquid on the semiconductor package in the chamber.

Abstract: A multi-channel transceiver includes a phase-locked loop circuit, a first transmitting channel and a second transmitting channel. The phase-locked loop circuit generates a first clock signal set and a second clock signal set with different frequencies. The first transmitting channel includes a first phase adjusting circuit and a first transmitter. The first phase adjusting circuit receives the first clock signal set and generates a first spread spectrum clock signal with a first SSCG profile. According to the first spread spectrum clock signal, the first transmitter generates a first serial data. The second transmitting channel includes a second phase adjusting circuit and a second transmitter. The second phase adjusting circuit receives the second clock signal set and generates a second spread spectrum clock signal with a second SSCG profile. According to the second spread spectrum clock signal, the second transmitter generates a second serial data.