Patents Assigned to Hitachi Hokkai Semiconductor, Ltd.
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Patent number: 6909179Abstract: A semiconductor device includes a substrate, a semiconductor chip mounted on one surface of the substrate, wherein the semiconductor chip has an integrated circuit and bonding pads formed on a main surface thereof. The main surface of the semiconductor chip has a quadrilateral shape with the bonding pads being disposed along four sides of the main surface. A plurality of conductors is disposed on the one surface of the substrate so as to surround the semiconductor chip along four sides thereof and a plurality of bonding wires electrically connect the bonding pads with tips of the conductors, respectively. A resin body seals the semiconductor chip, the conductors and the plurality of bonding wires. A pitch between adjacent bonding pads increases in a direction toward four corners defined by the four sides of the main surface of the semiconductor chip.Type: GrantFiled: July 16, 2001Date of Patent: June 21, 2005Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Shigeki Tanaka, Atsushi Fujisawa, Souichi Nagano, Tsugihiko Hirano, Ryouichi Oota, Takafumi Konno, Kenichi Tatebe, Toshiaki Okamoto
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Patent number: 6897093Abstract: Upon the manufacture of a non-leaded type semiconductor device having an encapsulater, and a gate cured resin and air vent cured resins which remain as a result of the exposure of leads and tub-suspension leads to a mounting surface of the encapsulater and the formation of the encapsulater, a groove through which a resin flows, is not provided over the full circumference of a cavity defined in a mold die for forming the encapsulater. A gate and air vents are provided outside an area in which no groove is defined. The flow of the resin between the cavity and each of the gate and air vents is made through a gap or space defined between each of the adjacent leads and each tub-suspension lead. If the leads and the tub-suspension leads are cut at a groove-free place, then the occurrence of resin waste and a resin crack can be restrained because the gate cured resin and the air vent cured resins have their surfaces which are identical to the leads and the tub-suspension leads and flat.Type: GrantFiled: July 25, 2003Date of Patent: May 24, 2005Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Takahiro Kasuga, Seiichi Tomihara, Kazuo Tasaka
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Patent number: 6887739Abstract: In a method of forming a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: GrantFiled: July 3, 2003Date of Patent: May 3, 2005Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
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Patent number: 6875639Abstract: A semiconductor chip has a quadrangle main surface, a wiring substrate, and a resin seal member for sealing the semiconductor chip, in which the resin seal member has a quadrangle main surface which confronts the main surface of the semiconductor chip. A gate cut trace portion is formed on a side face extending along a first side of the main surface of the resin seal member. A sectional area of an area between the main surface of the wiring substrate and the main surface of the resin seal member at a position outside a side face of the semiconductor chip is smaller than a sectional area of an area between the main surface of the semiconductor chip and the main surface of the resin seal member.Type: GrantFiled: March 7, 2002Date of Patent: April 5, 2005Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Hiroshi Arai, Nobuaki Nagashima, Norihiko Kasai, Isao Seki
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Patent number: 6838767Abstract: Provided is a technique which permits production of a semiconductor device having, integrated therein, a semiconductor chip smaller in external size than an ordinary semiconductor chip without lowering the production yield. The semiconductor device according to the present invention comprises a substrate having a square-shaped plane and having an interconnection formed on a first surface (chip mounting surface) of first and second opposite surfaces; a semiconductor chip which is mounted on the first surface of said substrate and has an electrode formed on a first surface (circuit forming surface) of first and second opposite surfaces of the semiconductor chip, and a conductive wire for electrically connecting the electrode of said semiconductor chip with the interconnection of said substrate, said interconnection having a plurality of connecting pads arranged from the peripheral side toward the inner side of said substrate.Type: GrantFiled: June 6, 2002Date of Patent: January 4, 2005Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Tsugihiko Hirano, Hidemi Ozawa
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Patent number: 6835596Abstract: An improvement of the yield of semiconductor devices is achieved in the manufacture of a semiconductor device. The method includes forming a resin enclosure for block-molding a plurality of a semiconductor chips by placing a plurality of semiconductor chips inside a cavity of a molding die along with a substrate, and then injecting a resin from a first side to a second side of a main surface of the substrate. The plurality of semiconductor chips are mounted on the main surface of the substrate from the first side to the second side of the main surface with a predetermined spacing, the second side facing the first side. The method is characterized by the application of cleaning treatment to the main surface of the substrate before forming the resin enclosure.Type: GrantFiled: September 28, 2001Date of Patent: December 28, 2004Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Masakatsu Gotou, Norihiko Kasai
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Patent number: 6832285Abstract: A microcomputer capable of on-board programming of dedicated user communication protocols without requiring a serial interface on the mounted board, and that will not destroy the dedicated user communication protocol code even if the system runs out of control. A user boot mat other than a user mat is provided for programming control programs for the user in the on-chip non-volatile memory of the microcomputer. The user boot mat serves as the mat for programming the dedicated user communication protocol and also provides a user boot mode for running the program. The user boot mat cannot program or erase in this user boot mode. By separating the user boot mat and user mat, an interface capable of programming and erasing the user-specified programming can be achieved without having to program a dedicated communication protocol on the user mat.Type: GrantFiled: February 25, 2002Date of Patent: December 14, 2004Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Naoki Yada, Eiichi Ishikawa
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Patent number: 6820179Abstract: A semiconductor device which has an internal circuit for performing a circuit operation corresponding to a signal inputted or outputted through an input/output interface circuit adapted to a serial bus. The semiconductor device has a non-volatile storage circuit for storing identification data. Internal identification data stored in the non-volatile storage circuit is compared with external identification data included in an input signal supplied through the serial bus by a comparator circuit. A control circuit is responsive to a match detecting signal generated by the comparator circuit to perform a circuit operation corresponding to an input signal subsequently supplied through the serial bus to change the internal identification data stored in the non-volatile storage circuit.Type: GrantFiled: December 4, 2001Date of Patent: November 16, 2004Assignees: Hitachi Hokkai Semiconductor, Ltd., Renesas Technology CorporationInventors: Nobuharu Kobayashi, Masanobu Kawamura, Toru Ishida, Masato Momii, Naoki Fujita
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Patent number: 6803258Abstract: In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate. Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w<t and p≦1.2t, with the inner leads secured to the heat radiation plate. The heat radiation plate has slits made therein to form radially shaped heat propagation paths between a semiconductor chip mounting area and the inner leads.Type: GrantFiled: May 23, 2002Date of Patent: October 12, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Fujio Ito, Hiroaki Tanaka, Hiromichi Suzuki, Tokuji Toida, Takafumi Konno, Kunihiro Tsubosaki, Shigeki Tanaka, Kazunari Suzuki, Akihiko Kameoka
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Patent number: 6800507Abstract: Upon the manufacture of a non-leaded type semiconductor device having an encapsulater, and a gate cured resin and air vent cured resins which remain as a result of the exposure of leads and tub-suspension leads to a mounting surface of the encapsulater and the formation of the encapsulater, a groove through which a resin flows is not provided over the full circumference of a cavity defined in a mold die for forming the encapsulater. A gate and air vents are provided outside an area in which no groove is defined. The flow of the resin between the cavity and each of the gate and air vents is made through a gap or space defined between each of the adjacent leads and each tub-suspension lead. If the leads and the tub-suspension leads are cut at a groove-free place, then the occurrence of resin waste and a resin crack can be restrained because the gate cured resin and the air vent cured resins have their surfaces which are flat and level with the leads and the tub-suspension leads.Type: GrantFiled: December 23, 2002Date of Patent: October 5, 2004Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Takahiro Kasuga, Seiichi Tomihara, Kazuo Tasaka
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Patent number: 6787395Abstract: Silicon chip having narrow pitches of Au bumps are mounted on a module substrate in such a way that while taking into consideration a difference in coefficient of thermal expansion between the silicon chip and the module substrate, a total pitch of electrode pads of the silicon chip is made narrower than a total pitch of the Au bumps, thereby preventing misregistration between the Au bumps and the electrode pads in the course of heat treatment to ensure reliable contact therebetween.Type: GrantFiled: October 15, 2002Date of Patent: September 7, 2004Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Yoshiyuki Kado, Tsukio Funaki, Hiroshi Kikuchi, Ikuo Yoshida
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Patent number: 6787442Abstract: By a solder bump, a CSP is bonded to a first electrode of the module substrate of a multi-chip module. For this solder bump, a solder added with an alkaline earth metal such as Ba, Be, Ca or Mg is used. Accordingly, upon solder reflow, phosphorous (P) reacts with the alkaline earth metal, thereby forming a P compound. Owing to dispersion of this P compound inside of the solder bump, no P concentrated layer is formed on the Ni film, making it possible to prevent peeling of the solder bump from the first electrode upon solder reflow. Thus, the present invention makes it possible to improve the solder bonding property.Type: GrantFiled: February 5, 2003Date of Patent: September 7, 2004Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventor: Tetsuya Hayashida
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Publication number: 20040166608Abstract: A method of manufacturing an electronic device including a first electronic component mounted on one main surface of a wiring board by being thermo-compression bonded by means of a thermo-compression bonding tool with an adhesive resin interposed between a first area of the one main surface of the wiring board and the first electronic component, and a second electronic component mounted on a second area different from the first area of the one main surface of the wiring board by melting a soldering paste material and higher than the first electronic component in post-mounting height, and wherein the first electronic component is mounted before the mounting of the second electronic component.Type: ApplicationFiled: March 2, 2004Publication date: August 26, 2004Applicants: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventor: Shigeru Nakamura
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Patent number: 6780677Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.Type: GrantFiled: August 21, 2002Date of Patent: August 24, 2004Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Satoshi Imasu, Ikuo Yoshida, Tetsuya Hayashida, Akira Yamagiwa, Shinobu Takeura
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Patent number: 6781234Abstract: By a solder bump, a CSP is bonded to a first electrode of the module substrate of a multi-chip module. For this solder bump, a solder added with an alkaline earth metal such as Ba, Be, Ca or Mg is used. Accordingly, upon solder reflow, phosphorous (P) reacts with the alkaline earth metal, thereby forming a P compound. Owing to dispersion of this P compound inside of the solder bump, no P concentrated layer is formed on the Ni film, making it possible to prevent peeling of the solder bump from the first electrode upon solder reflow. Thus, the present invention makes it possible to improve the solder bonding property.Type: GrantFiled: June 19, 2002Date of Patent: August 24, 2004Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventor: Tetsuya Hayashida
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Patent number: 6774831Abstract: An analog switch and an analog multiplexer are realized by which electron charges which have been stored in a stray capacitance provided on the output side thereof before a switch is conducted do not give an adverse influence to a level of such an analog input voltage which is subsequently entered after the switch has been switched. An analog switch circuit is arranged by insulating gate type transistors and a voltage follower which is parallel-connected to these insulating type transistors. When the analog switch circuit is turned ON, the voltage follower is firstly brought into an active state, and thereafter, these insulating gate type transistors are brought into conductive conditions.Type: GrantFiled: April 22, 2003Date of Patent: August 10, 2004Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventor: Yasuyuki Saito
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Patent number: 6767767Abstract: A semiconductor device manufacturing method is disclosed which can reduce the cost of manufacturing an MAP type semiconductor device. According to this method, a substrate with semiconductor chips mounted at predetermined intervals in a matrix shape on a main surface thereof is clamped between a lower mold and an upper mold of a molding die, an insulating resin is injected through gates into a cavity formed on the main surface side of the substrate, air present within the cavity is allowed to escape from air vents, to form a block molding package which covers the semiconductor chips, thereafter bump electrodes are formed on a back surface of the substrate, and then the block molding package and the substrate are cut longitudinally and transversely to fabricate plural semiconductor devices. The air vents are formed by grooves provided in the substrate.Type: GrantFiled: July 16, 2002Date of Patent: July 27, 2004Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Tetsuya Hayashida, Norihiko Kasai
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Patent number: 6764878Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: GrantFiled: July 12, 2002Date of Patent: July 20, 2004Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
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Patent number: 6759279Abstract: In a method of forming a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: GrantFiled: August 8, 2002Date of Patent: July 6, 2004Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
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Publication number: 20040104490Abstract: Upon the manufacture of a non-leaded type semiconductor device having an encapsulater, and a gate cured resin and air vent cured resins which remain as a result of the exposure of leads and tub-suspension leads to a mounting surface of the encapsulater and the formation of the encapsulater, a groove through which a resin flows, is not provided over the full circumference of a cavity defined in a mold die for forming the encapsulater. A gate and air vents are provided outside an area in which no groove is defined. The flow of the resin between the cavity and each of the gate and air vents is made through a gap or space defined between each of the adjacent leads and each tub-suspension lead. If the leads and the tub-suspension leads are cut at a groove-free place, then the occurrence of resin waste and a resin crack can be restrained because the gate cured resin and the air vent cured resins have their surfaces which are identical to the leads and the tub-suspension leads and flat.Type: ApplicationFiled: July 25, 2003Publication date: June 3, 2004Applicants: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Takahiro Kasuga, Seiichi Tomihara, Kazuo Tasaka