Patents Assigned to Hitachi Hokkai Semiconductor, Ltd.
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Patent number: 6461896Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.Type: GrantFiled: May 5, 2000Date of Patent: October 8, 2002Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Satoshi Imasu, Ikuo Yoshida, Tetsuya Hayashida, Akira Yamagiwa, Shinobu Takeura
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Patent number: 6448111Abstract: In a method of forming a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: GrantFiled: June 15, 2000Date of Patent: September 10, 2002Assignees: Hitachi Hokkai Semiconductor, Ltd., Hitachi, Ltd.Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
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Patent number: 6437428Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: GrantFiled: June 16, 2000Date of Patent: August 20, 2002Assignee: Hitachi Hokkai Semiconductor, Ltd.Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
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Patent number: 6396142Abstract: In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate. Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w<t and p≦1.2t, with the inner leads secured to the heat radiation plate. The heat radiation plate has slits made therein to form radially shaped heat propagation paths between a semiconductor chip mounting area and the inner leads.Type: GrantFiled: August 6, 1999Date of Patent: May 28, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Fujio Ito, Hiroaki Tanaka, Hiromichi Suzuki, Tokuji Toida, Takafumi Konno, Kunihiro Tsubosaki, Shigeki Tanaka, Kazunari Suzuki, Akihiko Kameoka
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Patent number: 6232650Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: GrantFiled: July 30, 1998Date of Patent: May 15, 2001Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
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Patent number: 6208525Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.Type: GrantFiled: March 26, 1998Date of Patent: March 27, 2001Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Satoshi Imasu, Ikuo Yoshida, Tetsuya Hayashida, Akira Yamagiwa, Shinobu Takeura
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Patent number: 5910010Abstract: A method of manufacturing a semiconductor integrated circuit device includes the steps of constructing a plurality of lead frames having leads which each include an inner portion and an outer portion and electrically connecting a semiconductor chip to the inner portions of the leads of each frame. The lead frames are then stacked one above each other to form a vertical stack and plates are then inserted between each of the lead frames with each plate having an opening in the center whereby a central cavity is formed in the stack. The stack is then placed between a top mold member and a bottom mold member and a resin is injected into the central cavity whereupon the resin is cured to form a single resin package encapsulating the semiconductor chips. The resin package is then released from the mold members.Type: GrantFiled: February 18, 1997Date of Patent: June 8, 1999Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp., Hitachi Tohbu Semiconductor, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Hirotaka Nishizawa, Tomoyoshi Miura, Ichirou Anjou, Masamichi Ishihara, Masahiro Yamamura, Sadao Morita, Takashi Araki, Kiyoshi Inoue, Toshio Sugano, Tetsuji Kohara, Toshio Yamada, Yasushi Sekine, Yoshiaki Anata, Masakatsu Goto, Norihiko Kasai, Shinobu Takeura, Mutsuo Tsukuda, Yasunori Yamaguchi, Jiro Sawada, Hidetoshi Iwai, Seiichiro Tsukui, Tadao Kaji, Noboru Shiozawa
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Patent number: 5684315Abstract: A semiconductor memory device has memory cells provided at intersections between word line conductors and data line conductors. Each of the memory cells includes a cell selecting transistor and an information storage capacitor. The capacitor in each of the memory cells includes a first capacitor component formed over the control electrode of the transistor and a second capacitor component formed over a word line conductor which is adjacent to a word line conductor integral with the control electrode of the transistor. Each of the first and second capacitor components has a common electrode, a storage electrode and a dielectric film sandwiched therebetween, and the storage electrode is at a level higher than the common electrode in each of said first and second capacitor components. The storage electrodes of the first and second capacitor components are electrically connected with each other and with one of the semiconductor regions of the transistor.Type: GrantFiled: December 23, 1994Date of Patent: November 4, 1997Assignees: Hitachi, Ltd., Hitachi Instruments Engineering Co., Ltd., Hitachi ULSI Engineering Corporation, Hitachi Hokkai Semiconductor, Ltd.Inventors: Hiroyuki Uchiyama, Yoshiyuki Kaneko, Hiroki Soeda, Yasuhide Fujioka, Nozomu Matsuda, Motoko Sawamura
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Patent number: 5440521Abstract: A semiconductor integrated circuit device constituted by a plurality of sets each of which having a pair of memory mats and each memory mat having a plurality of memory cells arranged in a matrix and a sense amplifier, I/O lines for transmitting signals provided by the sense amplifiers, selecting circuitry for selecting either a condition for sending out the signals provided by the sense amplifiers on the I/O lines or a condition for not sending out the same on the I/O lines, and Y-selection lines for transmitting the selection signals. A decoder connected with selection is disposed substantially at the middle of the Y-selection lines. X- and Y-address buffers are disposed close to each other nearer to the center of the chip than X- and Y-redundant circuits. A reference voltage generating circuit is disposed nearer to the edge of the chip than an output buffer circuit. A relief selecting circuit of each memory mat is formed adjacent to a redundant line selecting circuits included in the same memory mat.Type: GrantFiled: August 19, 1993Date of Patent: August 8, 1995Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Manabu Tsunozaki, Kyoko Ishii, Koichi Nozaki, Hiroshi Yoshioka, Yoshihisa Koyama, Shinji Udo, Hidetomo Aoyagi, Sinichi Miyatake, Makoto Morino, Akihiko Hoshida
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Patent number: 5219794Abstract: In a chip carrier wherein a semiconductor chip is face down bonded to a package substrate through solder bumps, then covered with a cap and sealed hermetically using a sealing solder, the back of the semiconductor chip being bonded closely to the underside of the cap using a solder for heat transfer, a solder preform serving as the said heat transfer solder is heat-melted and a portion of the thus melted solder is allowed to flow into the sealing portion to effect the hermetic seal of the chip. Furthermore, in order to improve the flowability of the solder preform during the melt flow thereof, a metallized layer for heat transfer formed under the heat transfer solder of the cap and a sealing metallized layer are partially connected with each other through a connecting metallized layer.Type: GrantFiled: March 13, 1992Date of Patent: June 15, 1993Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Toshihiko Satoh, Tetsuya Hayashida, Hiroshi Kikuchi, Takeo Yamada, Takashi Mori