Patents Assigned to Hitachi Hokkai Semiconductor, Ltd.
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Patent number: 6737741Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.Type: GrantFiled: August 21, 2002Date of Patent: May 18, 2004Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Satoshi Imasu, Ikuo Yoshida, Tetsuya Hayashida, Akira Yamagiwa, Shinobu Takeura
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Patent number: 6727119Abstract: A projection is formed adjacent an inner periphery wall of a recess of a ceramic substrate and a nozzle is disposed so as to overhang corners of a first face of the projection. Thereafter, resin is dropped from the nozzle onto the corners of the projection, whereby the resin flows down along the corners onto a resin passage. After passing the resin passage, the resin is admitted between a bottom of the ceramic substrate and a driver to effect underfill sealing. Positioning the nozzle above the corners of the projection can be controlled relatively easily.Type: GrantFiled: September 20, 2002Date of Patent: April 27, 2004Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventor: Takaki Saitou
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Patent number: 6722028Abstract: A method of manufacturing an electronic device including a first electronic component mounted on one main surface of a wiring board by being thermo-compression bonded by means of a thermo-compression bonding tool with an adhesive resin interposed between a first area of the one main surface of the wiring board and the first electronic component, and a second electronic component mounted on a second area different from the first area of the one main surface of the wiring board by melting a soldering paste material and higher than the first electronic component in post-mounting height, and wherein the first electronic component is mounted before the mounting of the second electronic component.Type: GrantFiled: February 4, 2003Date of Patent: April 20, 2004Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventor: Shigeru Nakamura
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Patent number: 6713849Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.Type: GrantFiled: November 20, 2001Date of Patent: March 30, 2004Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
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Publication number: 20040056337Abstract: A non-leaded type semiconductor device comprising a tab, tab suspension leads, plural leads, the tab, the tab suspension leads and the plural leads being exposed to one surface of the seal member, a semiconductor element positioned within the seal member and fixed to a surface of the tab with an adhesive, electrically conductive wires for electrically connecting electrodes on the semiconductor element and the leads with each other, and electrically conductive wires for electrically connecting the electrodes on the semiconductor element and a tab surface portion deviated from the semiconductor element with each other, wherein the tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element, a groove is formed in the tab surface portion positioned between a semiconductor element fixing area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove bType: ApplicationFiled: September 22, 2003Publication date: March 25, 2004Applicant: HITACHI, LTD. and HITACHI HOKKAI SEMICONDUCTOR, LTD.Inventors: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
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Publication number: 20040043537Abstract: Peeling between a molding resin and a substrate is to be prevented to improve the quality of a semiconductor device. A film substrate capable of being deformed following shrinkage on curing of a molding resin and having plural partitioned device areas is provided, then a block molding is performed so as to cover the plural device areas in a lump on a chip bearing surface side of the film substrate, and thereafter the film substrate is subjected to dicing wherein a cutting blade is advanced toward a block molding portion to divide the film substrate device area by device area in accordance with a down cutting method, whereby peeling of the substrate in the dicing work can be prevented.Type: ApplicationFiled: September 4, 2003Publication date: March 4, 2004Applicants: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventor: Seiichi Tomihara
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Patent number: 6673655Abstract: In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate. Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w<t and p≦1.2t, with the inner leads secured to the heat radiation plate. The heat radiation plate has slits made therein to form radially shaped heat propagation paths between a semiconductor chip mounting area and the inner leads.Type: GrantFiled: May 23, 2002Date of Patent: January 6, 2004Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Fujio Ito, Hiroaki Tanaka, Hiromichi Suzuki, Tokuji Toida, Takafumi Konno, Kunihiro Tsubosaki, Shigeki Tanaka, Kazunari Suzuki, Akihiko Kameoka
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Patent number: 6649448Abstract: Peeling between a molding resin and a substrate is prevented to improve the quality of a semiconductor device. A film substrate capable of being deformed following shrinkage upon curing of a molding resin and having plural partitioned device areas is provided. Then, a block molding is performed so as to cover the plural device areas in a lump on a chip bearing surface side of the film substrate. Thereafter the film substrate is subjected to dicing wherein a cutting blade is advanced toward a block molding portion to divide the film substrate device area by device area in accordance with a down cutting method, whereby peeling of the substrate in the dicing work can be prevented.Type: GrantFiled: September 25, 2001Date of Patent: November 18, 2003Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventor: Seiichi Tomihara
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Publication number: 20030201818Abstract: An analog switch and an analog multiplexer are realized by which electron charges which have been stored in a stray capacitance provided on the output side thereof before a switch is conducted do not give an adverse influence to a level of such an analog input voltage which is subsequently entered after the switch has been switched. An analog switch circuit is arranged by insulating gate type transistors and a voltage follower which is parallel-connected to these insulating type transistors. When the analog switch circuit is turned ON, the voltage follower is firstly brought into an active state, and thereafter, these insulating gate type transistors are brought into conductive conditions.Type: ApplicationFiled: April 22, 2003Publication date: October 30, 2003Applicants: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventor: Yasuyuki Saito
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Patent number: 6638779Abstract: A probe inspection system is used in integrated circuit fabrication and testing, using a network, including probers, testers, manufacturing specification management, testing step control and test results management, which has a modified prober software. Lots are set successively to cassettes, and when the lot in another cassette is set after the end of processing of the lot in one cassette, processing of the next lot is executed automatically. Continuous lot inspection can be effected by repeating these operations. Even during processing of the next lot, it is always possible to change lot in the processing-completed cassette and input data, such as lot No. In probe check in wafer testing, it is possible to diminish the working load and the waiting of workers in the lot change, reduce the number of cassettes and improve the working efficiency of testers.Type: GrantFiled: March 14, 2002Date of Patent: October 28, 2003Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventor: Tomohiro Taira
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Patent number: 6590275Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: GrantFiled: January 31, 2002Date of Patent: July 8, 2003Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
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Publication number: 20030107909Abstract: There is provided a control circuit which instructs, using a control signal, validation and invalidation of operations of an input/output interface circuit suitable for a bus such as the IIC bus and maintains an output element included in the input/output interface circuit to the OFF stage without relation to voltage change at the external terminal corresponding to the input/output interface circuit in response to invalidation of operation due to the control signal. Accordingly, a semiconductor device which can be used flexibly with a simplified structure and prevents erroneous output in the output circuit corresponding to the IIC bus can be obtained.Type: ApplicationFiled: September 27, 2002Publication date: June 12, 2003Applicants: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventor: Hirotsugu Nakamura
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Patent number: 6577263Abstract: An analog switch and an analog multipleplexer are realized by which electron charges which have been stored in a stray capacitance provided on the output side thereof before a switch is conducted do not give an adverse influence to a level of such an analog input voltage which is subsequently entered after the switch has been switched. An analog switch circuit is arranged by insulating gate type transistors and a voltage follower which is parallel-connected to these insulating type transistors. When the analog switch circuit is turned ON, the voltage follower is firstly brought into an active state, and thereafter, these insulating gate type transistors are brought into conductive conditions.Type: GrantFiled: October 30, 2002Date of Patent: June 10, 2003Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventor: Yasuyuki Saito
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Patent number: 6553660Abstract: A method of manufacturing an electronic device including a first electronic component mounted on one main surface of a wiring board by being thermo-compression bonded by means of a thermo-compression bonding tool with an adhesive resin interposed between a first area of the one main surface of the wiring board and the first electronic component, and a second electronic component mounted on a second area different from the first area of the one main surface of the wiring board by melting a soldering paste material and higher than the first electronic component in post-mounting height, and wherein the first electronic component is mounted before the mounting of the second electronic component.Type: GrantFiled: August 23, 2001Date of Patent: April 29, 2003Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventor: Shigeru Nakamura
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Patent number: 6551862Abstract: A semiconductor device is disclosed, comprising a tape substrate which supports a semiconductor chip, an insulating adhesive layer disposed between the semiconductor chip and the tape substrate, an insulating sheet member laminated to the insulating adhesive layer and formed harder than the insulating adhesive layer, wires for connecting pads on the semiconductor chip with connecting terminals on the tape substrate, a sealing portion formed by sealing the semiconductor chip with resin, and plural solder balls provided on a back of the tape substrate. A die bonding layer for fixing the semiconductor chip thereto is composed of an insulating adhesive layer and the insulating sheet member laminated thereto. The die bonding layer is formed thick by such a multi-layer structure, whereby the resin balance of the surface and back of the semiconductor chip is improved to prevent warping of a package and improve the mounting temperature cyclicity and reflow characteristic.Type: GrantFiled: October 18, 2001Date of Patent: April 22, 2003Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Riyouichi Oota, Tsugihiko Hirano, Atsushi Fujisawa, Takafumi Konno
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Patent number: 6509860Abstract: An analog switch and an analog multiplexer are realized by which electron charges which have been stored in a stray capacitance provided on the output side thereof before a switch is conducted do not give an adverse influence to a level of such an analog input voltage which is subsequently entered after the switch has been switched. An analog switch circuit is arranged by insulating gate type transistors and a voltage follower which is parallel-connected to these insulating type transistors. When the analog switch circuit is turned ON, the voltage follower is firstly brought into an active state, and thereafter, these insulating gate type transistors are brought into conductive conditions.Type: GrantFiled: September 25, 2001Date of Patent: January 21, 2003Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventor: Yasuyuki Saito
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Publication number: 20020192865Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.Type: ApplicationFiled: August 21, 2002Publication date: December 19, 2002Applicant: HITACHI, LTD. and HITACHI HOKKAI SEMICONDUCTOR, LTD.Inventors: Satoshi Imasu, Ikuo Yoshida, Tetsuya Hayashida, Akira Yamagiwa, Shinobu Takeura
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Patent number: 6489181Abstract: Silicon chip having narrow pitches of Au bumps are mounted on a module substrate in such a way that while taking into consideration a difference in coefficient of thermal expansion between the silicon chip and the module substrate, a total pitch of electrode pads of the silicon chip is made narrower than a total pitch of the Au bumps, thereby preventing misregistration between the Au bumps and the electrode pads in the course of heat treatment to ensure reliable contact therebetween.Type: GrantFiled: July 3, 2001Date of Patent: December 3, 2002Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Yoshiyuki Kado, Tsukio Funaki, Hiroshi Kikuchi, Ikuo Yoshida
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Patent number: 6476466Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: GrantFiled: January 31, 2002Date of Patent: November 5, 2002Assignee: Hitachi Hokkai Semiconductor, Ltd.Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
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Patent number: 6472749Abstract: Provided is a technique which permits production of a semiconductor device having, integrated therein, a semiconductor chip smaller in external size than an ordinary semiconductor chip without lowering the production yield. The semiconductor device according to the present invention comprises a substrate having a square-shaped plane and having an interconnection formed on a first surface (chip mounting surface) of first and second opposite surfaces; a semiconductor chip which is mounted on the first surface of said substrate and has an electrode formed on a first surface (circuit forming surface) of first and second opposite surfaces of the semiconductor chip, and a conductive wire for electrically connecting the electrode of said semiconductor chip with the interconnection of said substrate, said interconnection having a plurality of connecting pads arranged from the peripheral side toward the inner side of said substrate.Type: GrantFiled: February 2, 2000Date of Patent: October 29, 2002Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Tsugihiko Hirano, Hidemi Ozawa