Abstract: A method for trimming a structure obtained by bonding a first wafer to a second waver on contact faces and thinning the first waver, wherein at least either the first wafer or the second wafer is chamfered and thus exposes the edge of the contact face of the first wafer, wherein the trimming concerns the first wafer. The method includes a) selecting the second wafer from among wafers with a resistance to a chemical etching planned in b) that is sufficient with respect to the first wafer to allow b) to be carried out; b) after bonding the first wafer to the second wafer, chemical etching the edge of the first wafer to form in the first wafer a pedestal resting entirely on the contact face of the second wafer and supporting the remaining of the first wafer; and c) thinning the first wafer until the pedestal is reached and attacked, to provide a thinned part of the first wafer.

Abstract: A sealing and/or anchoring element for use in pipelines. The sealing and/or anchoring element includes at least one helical element disposed around a string section, with the helical element being configured so as to be able to expand radially towards an inner wall of the pipeline as the circumferential diameter thereof is increased.

Abstract: Three dimensionally integrated semiconductor systems include a photoactive device operationally coupled with a current/voltage converter on a semiconductor-on-insulator (SeOI) substrate. An optical interconnect is operatively coupled to the photoactive device. A semiconductor device is bonded over the SeOI substrate, and an electrical pathway extends between the current/voltage converter and the semiconductor device bonded over the SeOI substrate. Methods of forming such systems include forming a photoactive device on an SeOI substrate, and operatively coupling an waveguide with the photoactive device. A current/voltage converter may be formed over the SeOI substrate, and the photoactive device and the current/voltage converter may be operatively coupled with one another. A semiconductor device may be bonded over the SeOI substrate and operatively coupled with the current/voltage converter.

Abstract: Methods of forming bonded semiconductor structures include providing a substrate structure including a relatively thinner layer of material on a thicker substrate body, and forming a plurality of through wafer interconnects through the layer of material. A first semiconductor structure may be bonded over the thin layer of material, and at least one conductive feature of the first semiconductor structure may be electrically coupled with at least one of the through wafer interconnects. A transferred layer of material may be provided over the first semiconductor structure on a side thereof opposite the first substrate structure, and at least one of an electrical interconnect, an optical interconnect, and a fluidic interconnect may be formed in the transferred layer of material. A second semiconductor structure may be provided over the transferred layer of material on a side thereof opposite the first semiconductor structure. Bonded semiconductor structures are fabricated using such methods.

Abstract: Methods of forming bonded semiconductor structures include forming through wafer interconnects through a layer of material of a first substrate structure, bonding one or more semiconductor structures over the layer of material, and electrically coupling the semiconductor structures with the through wafer interconnects. A second substrate structure may be bonded over the processed semiconductor structures on a side thereof opposite the first substrate structure. A portion of the first substrate structure then may be removed, leaving the layer of material with the through wafer interconnects therein attached to the processed semiconductor structures. At least one through wafer interconnects then may be electrically coupled to a conductive feature of another structure, after which the second substrate structure may be removed. Bonded semiconductor structures are formed using such methods.

Abstract: A stem 8 has the following elements made from FRP: an upper outer shell 4U, a main structure upper half 3U, a main structure lower half 3L, and a lower outer shell 4L when the stem is placed in a flat state. The elements are integrated into one piece by stacking the elements and applying heat and pressure to melt resins impregnated in the FRP structural elements. Each outer shell is a curved prepreg sheet formed by impregnating carbon fibers arranged at angle of ±45 degrees with a thermoplastic resin, and each upper and lower halve is an evenly stacked part in which prepreg sheets are stacked. Overlapping section 5 of the upper and lower outer shells are formed such that the left and right portions of a main structure 3 formed by integrating the upper and lower halves 3U, 3L does not have a stepped outer surface.

Abstract: Methods of directly bonding a first semiconductor structure to a second semiconductor structure include directly bonding at least one device structure of a first semiconductor structure to at least one device structure of a second semiconductor structure in a conductive material-to-conductive material direct bonding process. In some embodiments, at least one device structure of the first semiconductor structure may be caused to project a distance beyond an adjacent dielectric material on the first semiconductor structure prior to the bonding process. In some embodiments, one or more of the device structures may include a plurality of integral protrusions that extend from a base structure. Bonded semiconductor structures are fabricated using such methods.

Abstract: A method for trimming a structure obtained by bonding a first wafer to a second waver on contact faces and thinning the first waver, wherein at least either the first wafer or the second wafer is chamfered and thus exposes the edge of the contact face of the first wafer, wherein the trimming concerns the first wafer. The method includes a) selecting the second wafer from among wafers with a resistance to a chemical etching planned in b) that is sufficient with respect to the first wafer to allow b) to be carried out; b) after bonding the first wafer to the second wafer, chemical etching the edge of the first wafer to form in the first wafer a pedestal resting entirely on the contact face of the second wafer and supporting the remaining of the first wafer; and c) thinning the first wafer until the pedestal is reached and attacked, to provide a thinned part of the first wafer.

Abstract: A packer for sealing against an inner cylindrical mandrel and a wellbore wall.

Abstract: Method for forming a semi-conducting structure includes the formation of at least one part of a circuit or a component, in or on a superficial layer of a substrate, the substrate including a buried layer underneath the superficial layer, and an underlying layer serving as first support, a transfer of said substrate onto a handle substrate, and then an elimination of the first support, the formation of an electrically conducting or ground plane forming layer, on at least one part of said buried layer, the formation, on said electrically conducting or ground plane forming layer, of a bonding layer, a transfer of the structure obtained onto a second support and an elimination of said handle substrate.

Abstract: A method of implanting atoms and/or ions into a substrate, including: a) a first implantation of ions or atoms at a first depth in the substrate, to form a first implantation plane, b) at least one second implantation of ions or atoms at a second depth in the substrate, which is different from the first depth, to form at least one second implantation plane.

Abstract: Methods of forming bonded semiconductor structures include providing a first semiconductor structure including a device structure, bonding a second semiconductor structure to the first semiconductor structure below about 400° C., forming a through wafer interconnect through the second semiconductor structure and into the first semiconductor structure, and bonding a third semiconductor structure to the second semiconductor structure on a side thereof opposite the first semiconductor structure. In additional embodiments, a first semiconductor structure is provided. Ions are implanted into a second semiconductor structure. The second semiconductor structure is bonded to the first semiconductor structure.

Abstract: Methods of forming semiconductor devices include providing a substrate including a layer of semiconductor material on a layer of electrically insulating material. A first metallization layer is formed over a first side of the layer of semiconductor material. Through wafer interconnects are formed at least partially through the substrate. A second metallization layer is formed over a second side of the layer of semiconductor material opposite the first side thereof. An electrical pathway is provided that extends through the first metallization layer, the substrate, and the second metallization layer between a first processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material and a second processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material. Semiconductor structures are fabricated using such methods.

Abstract: Methods of bonding together semiconductor structures include annealing a first metal feature on a first semiconductor structure, bonding the first metal feature to a second metal feature of a second semiconductor structure to form a bonded metal structure that comprises the first metal feature and the second metal feature, and annealing the bonded metal structure. Annealing the first metal feature may comprise subjecting the first metal feature to a pre-bonding thermal budget, and annealing the bonded metal structure may comprise subjecting the bonded metal structure to a post-bonding thermal budget that is less than the pre-bonding thermal budget. Bonded semiconductor structures are fabricated using such methods.

Abstract: Methods of bonding together semiconductor structures include annealing metal of a feature on a semiconductor structure prior to directly bonding the feature to a metal feature of another semiconductor structure to form a bonded metal structure, and annealing the bonded metal structure after the bonding process. The thermal budget of the first annealing process may be at least as high as a thermal budget of a later annealing process. Additional methods involve forming a void in a metal feature, and annealing the metal feature to expand the metal of the feature into the void. Bonded semiconductor structures and intermediate structures are formed using such methods.

Abstract: A process of forming a rough interface in a semiconductor substrate. The process includes the steps of depositing a material on a surface of the substrate, forming a zone of irregularities in the material, and forming a rough interface in the semiconductor substrate by a thermal oxidation of the material and a part of the substrate. Additionally, the surface of the oxidized material may be prepared and the surface may be assembled with a second substrate.

Abstract: An artificial cement-less hip prosthesis stem comprises an inner construct 7 which reacts with a load acting on a hip joint and an outer construct 8 for transmitting the load acting on the inner construct to a femur 1. The inner construct has an inner body 7B which reacts with the load transmitted from a neck 7A. The outer construct has both an outer body 8A which is bell mouth-shaped toward an epiphysis so as to surround the inner body 7B and a leg 8B extending toward a medullary cavity. The torsional rigidity given to the proximal end and the distal end of the outer body 8A and the leg 8B is regulated so as to be lower than the torsional rigidity given to an intermediate portion 18 of the outer body 8A.

Abstract: Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. An In-III-V semiconductor layer is grown with an Indium concentration above a saturation regime by adjusting growth conditions such as a temperature of a growth surface to create a super-saturation regime wherein the In-III-V semiconductor layer will grow with a diminished density of V-pits relative to the saturation regime.

Abstract: Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate a semiconductor substrate by forming a weakened zone in a donor structure at a predetermined depth to define a transfer layer between an attachment surface and the weakened zone and a residual donor structure between the weakened zone and a surface opposite the attachment surface. A metallic layer is formed on the attachment surface and provides an ohmic contact between the metallic layer and the transfer layer, a matched Coefficient of Thermal Expansion (CTE) for the metallic layer that closely matches a CTE of the transfer layer, and sufficient stiffness to provide structural support to the transfer layer. The transfer layer is separated from the donor structure at the weakened zone to form a composite substrate comprising the transfer layer the metallic layer.

Abstract: The invention relates to a process of bonding by molecular adhesion of two layers, such as wafers of semiconductor material, wherein propagation of a first bonding wave is initiated from a pressure point applied to at least one of the two layers, and wherein the first bonding wave step is followed by propagating a second bonding wave over an area, for example, in the vicinity of the pressure point. Propagation of the second bonding wave may be obtained through the interposing of a separation element between the two wafers and the withdrawal of the element, for example, after the beginning of the first bonding wave propagation.