Patents Assigned to I-TEC AS
  • Patent number: 8093077
    Abstract: The present invention relates to a method for manufacturing a crack free monocrystalline nitride layer having the composition AlxGa1-xN, where 0?x?0.3, on a substrate that is likely to generate tensile stress in the layer and to structures containing such layer and substrate. The method includes forming a nucleation layer on the substrate; forming a monocrystalline intermediate layer of aluminum or gallium nitride at a selected thickness on the nucleation layer; forming a monocrystalline seed layer of an AlBN compound in which the boron content is between 0 and 10% at a selected temperature and thickness on the intermediate layer with the thicknesses of the seed and intermediate layers being in a ratio of between 0.05 and 1; and forming the monocrystalline nitride layer of AlxGa1-xN nitride at a selected temperature on the seed layer, with the temperature of formation of the seed layer being 50 to 150° C.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: January 10, 2012
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventor: Hacene Lahreche
  • Patent number: 8093138
    Abstract: A method of forming an epitaxially grown layer by forming a region of weakness in a support substrate to define a support portion and a remainder portion on opposite sides of the region of weakness, epitaxially growing an epitaxially grown layer on the support portion after forming the region of weakness but prior to detachment of the support portion from the remainder portion; bonding the epitaxially grown layer to an acceptor substrate before detaching the remainder portion from the support portion; and detaching the remainder portion from the support portion at the region of weakness. The epitaxially grown layer may be removed from the support portion as a free-standing structure.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: January 10, 2012
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bruce Faure, Lea Di Cioccio
  • Patent number: 8093686
    Abstract: A process for obtaining a hybrid substrate that includes at least one active layer of Group III/N material for applications in the field of electronics, optics, photovoltaics or optoelectronics. The method includes selecting a source substrate of Group III/N material having a hexagonal single crystal crystallographic structure; carrying out an implantation of He+ helium ions into the source substrate through an implantation face which lies in a plane approximately parallel with the “c” crystallographic axis of the material, at an implantation dose equal to or greater than 1×1016 He+/cm2 and 1×1017 He+/cm2, to form therein a number of nanocavities defining a weakened zone which delimits the active layer; and transferring the active layer by applying an overall energy budget capable of causing detachment of the layer from the source substrate, wherein the budget also causes the nanocavities to grow into cavities.
    Type: Grant
    Filed: September 1, 2008
    Date of Patent: January 10, 2012
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventor: Arnaud Garnier
  • Patent number: 8093687
    Abstract: Methods for transferring of a useful layer from a support are described. In an embodiment, the method includes for facilitating transfer of a useful layer from a support by providing an interface in a first support to define a useful layer; and forming a peripheral recess on the first support below the interface so that the periphery of the interface is exposed to facilitate removal and transfer of the useful layer. An epitaxial layer can be formed on the useful layer after forming the recess, with the width and depth of the recess being sufficient to accommodate the volume of residual material resulting from formation of the epitaxial layer without covering the periphery of the interface. Alternatively, an epitaxial layer can be formed on the useful layer after forming the recess, wherein the peripheral recess is configured for receiving sufficient residual material from the epitaxial layer to prevent bonding between the residual material and the useful layer.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: January 10, 2012
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Fabrice Letertre, Olivier Rayssac
  • Patent number: 8091601
    Abstract: The invention relates to equipment for carrying out a process for bonding by molecular adhesion of two substrates to one another during which the surfaces of the substrates are placed in close contact and bonding occurs by propagation of a bonding front between the substrates. The invention includes, prior to bonding, a step of modifying the surface state of one or both of the surfaces of the substrates so as to regulate the propagation speed of the bonding front. The surface can be modified by locally or uniformly heating or roughening the surface(s) of the substrate(s).
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: January 10, 2012
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Sebastien Kerdiles, Carine Duret, Alexandre Vaufredaz, Frédéric Metral
  • Patent number: 8088671
    Abstract: A method of detaching two substrates at the embrittlement zone situated at a given depth of one of the two substrates. The method includes a separation annealing step implemented in a furnace, wherein the annealing includes a first phase during which the temperature changes along an upgrade allowing a high temperature to be reached and annealing at this high temperature to be stabilized, and a second phase during which the temperature changes along a downgrade, at the end of which the furnace is opened to unload the substrates from the furnace. The second phase is regulated so as to minimize temperature inhomogeneities such as cleavage defects at the detached surfaces of the substrates when the furnace is opened.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: January 3, 2012
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Walter Schwarzenbach, Nadia Ben Mohamed, Fleur Guittard
  • Patent number: 8083115
    Abstract: An automatic cutting device is described for cutting an assembly. The assembly includes a material having a weakened zone therein that defines a useful layer and being attached to a source substrate. The cutting device includes a cutting mechanism and a holding and positioning mechanism operatively associated with the cutting mechanism. The holding and positioning mechanism positions the material so that the cutting mechanism detaches the layer from the source substrate along the weakened zone. The cutting device also includes a control mechanism for adjusting at least two different portions of the assembly during detachment of the layer to facilitate a more precise detachment.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: December 27, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Olivier Rayssac, Fabrice Letertre
  • Patent number: 8084784
    Abstract: The invention relates to a method for forming a semiconductor heterostructure by providing a substrate with a first in-plane lattice parameter a1, providing a buffer layer with a second in-plane lattice parameter a2 and providing a top layer over the buffer layer. In order to improve the surface roughness of the semiconductor heterostructure, an additional layer is provided in between the buffer layer and the top layer, wherein the additional layer has a third in-plane lattice parameter a3 which is in between the first and second lattice parameters.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: December 27, 2011
    Assignee: S.O.I. Tec Silicon on Insulator Technologies
    Inventors: Christophe Figuet, Mark Kennard
  • Publication number: 20110312156
    Abstract: In order to reduce and render uniform the surface roughness and variations in thickness of a layer after detachment (post-fracture) of a donor substrate, the mean temperature of the donor substrate during implantation thereof is controlled so as to be in the range 20° C. to 150° C. with a maximum temperature variation of less than 30° C.
    Type: Application
    Filed: March 26, 2009
    Publication date: December 22, 2011
    Applicant: S.O.I. Tec Silicon on Insulator Technologies
    Inventors: Sébastien Cattet, Lise Guerrini, Nadia Ben Mohamed, Benjamin Scarfogliere
  • Publication number: 20110305835
    Abstract: Systems and methods for the gas treatment of one or more substrates include at least two gas injectors in a reaction chamber, one of which may be movable. The systems may also include a substrate support structure for holding one or more substrates disposed within the reaction chamber. The movable gas injector may be disposed between the substrate support structure and another gas injector. The gas injectors may be configured to discharge different process gasses therefrom. The substrate support structure may be rotatable around an axis of rotation.
    Type: Application
    Filed: June 14, 2010
    Publication date: December 15, 2011
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Ronald Thomas Bertram, JR., Chantal Arena, Ed Lindow
  • Patent number: 8076219
    Abstract: A process for reducing or suppressing the appearance of watermarks in a hydrophobic surface of a semiconductor substrate prepared as a base substrate for epitaxial growth. The process includes cleaning the hydrophobic surface of the semiconductor substrate with an aqueous solution containing hydrofluoric acid (HF) and an additional acid having a pKa of less than 3, preferably hydrochloric acid (HCl), wherein the additional acid is present in the solution at a concentration by weight that is less than that of the HF; and final rinsing the cleaned hydrophobic surface of the semiconductor substrate with deionised water while subjecting the hydrophobic surface of the semiconductor substrate to megasonic waves for a time sufficient to reduce or suppress watermarks that could otherwise occur on the hydrophobic surface if the megasonic waves were not applied.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: December 13, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventor: Khalid Radouane
  • Publication number: 20110294245
    Abstract: The invention relates to a method of adapting the lattice parameter of a seed layer of a strained material, comprising the following successive steps: a) a structure is provided that has a seed layer of strained material, of lattice parameter A1, of nominal lattice parameter An and of thermal expansion coefficient CTE3, a low-viscosity layer and an intermediate substrate of thermal expansion coefficient CTE1; b) a heat treatment is applied so as to relax the seed layer of strained material; and c) the seed layer is transferred onto a support substrate of thermal expansion coefficient CTE5, the intermediate substrate and the support substrate being chosen so that A1<An and CTE1?CTE3 and CTE5>CTE1 or A1>An and CTE1?CTE3 and CTE5<CTE1.
    Type: Application
    Filed: February 15, 2010
    Publication date: December 1, 2011
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Pascal Guenard, Frederic Dupont
  • Publication number: 20110291247
    Abstract: The present invention relates to a method for the formation of an at least partially relaxed strained material layer, the method comprising the steps of providing a seed substrate; patterning the seed substrate; growing a strained material layer on the patterned seed substrate; transferring the strained material layer from the patterned seed substrate to an intermediate substrate; and at least partially relaxing the strained material layer by a heat treatment.
    Type: Application
    Filed: January 11, 2010
    Publication date: December 1, 2011
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Fabrice Letertre, Bruce Faure, Pascal Guenard
  • Patent number: 8067298
    Abstract: The invention relates to methods of fabricating a layer of at least partially relaxed material, such as for electronics, optoelectronics or photovoltaics. An exemplary method includes supplying a structure that includes a layer of strained material situated between a reflow layer and a stiffener layer. The method further includes applying a heat treatment that brings the reflow layer to a temperature equal to or greater than the glass transition temperature of the reflow layer, and the thickness of the stiffener layer is progressively reduced during heat treatment. The invention also relates to an exemplary method of fabricating semiconductor devices on a layer of at least partially relaxed material. Specifically, at least one active layer may be formed on the at least partially relaxed material layer. The active layer may include laser components, photovoltaic components and/or electroluminescent diodes.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: November 29, 2011
    Assignee: S.O.I.TEC Silicon on Insulator Technologies
    Inventor: Oleg Kononchuk
  • Publication number: 20110287604
    Abstract: The invention relates to a method of initiating molecular bonding, comprising bringing one face of a first wafer to face one face of a second wafer and initiating a point of contact between the two facing faces. The point of contact is initiated by application to one of the two wafers, for example using a bearing element of a tool, of a mechanical pressure in the range 0,1 MPa to 33.3 MPa.
    Type: Application
    Filed: August 1, 2011
    Publication date: November 24, 2011
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Arnaud Castex, Marcel Broekaart
  • Publication number: 20110284863
    Abstract: Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation.
    Type: Application
    Filed: March 23, 2011
    Publication date: November 24, 2011
    Applicants: Arizona Board of Regents for and on Behalf of Arizona State University, S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Ed Lindow, Chantal Arena, Ronald Bertram, Ranjan Datta, Subhash Mahajan
  • Publication number: 20110287571
    Abstract: A method of fabricating a back-illuminated image sensor that includes the steps of providing a first substrate of a semiconductor layer, in particular a silicon layer, forming electronic device structures over the semiconductor layer and, only then, doping the semiconductor layer. By doing so, improved dopant profiles and electrical properties of photodiodes can be achieved such that the final product, namely an image sensor, has a better quality.
    Type: Application
    Filed: September 22, 2009
    Publication date: November 24, 2011
    Applicant: S.O.I.TEC Silicon On Insulator Technologies
    Inventors: Konstantin Bourdelle, Carlos Mazure
  • Patent number: 8062564
    Abstract: Method for fabricating a structure in the form of a plate, and structure in the form of a plate, in particular formed from silicon, including at least one substrate, a superstrate and at least one intermediate layer interposed between the substrate and the superstrate, in which the intermediate layer comprises at least one base material having distributed therein atoms or molecules termed extrinsic atoms or molecules which differ from the atoms or molecules of the base material, and in which a heat treatment is applied to said plate so that, in the temperature range of said heat treatment, the intermediate layer is plastically deformable and the presence of the selected extrinsic atoms or molecules in the selected base material causes the irreversible formation of micro-bubbles or micro-cavities in the intermediate layer.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: November 22, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventor: Michel Bruel
  • Patent number: 8062957
    Abstract: The invention relates to a method for preparing a surface of a semiconductor substrate by oxidizing the surface of the semiconductor substrate to thereby transform the natural oxide into an artificial oxide and then removing the artificial oxide, in particular to obtain an oxide-free substrate surface.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: November 22, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventor: Radouane Khalid
  • Publication number: 20110278691
    Abstract: The invention relates to a method of initiating molecular bonding, comprising bringing one face (31) of a first wafer (30) to face one face (21) of a second wafer (20) and initiating a point of contact between the two facing faces. The point of contact is initiated by application to one of the two wafers, for example using a bearing element (51) of a tool (50), of a mechanical pressure in the range 0.1 MPa to 33.3 MPa.
    Type: Application
    Filed: August 1, 2011
    Publication date: November 17, 2011
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Arnaud Castex, Marcel Broekaart