Patents Assigned to I-TEC AS
  • Publication number: 20120187541
    Abstract: The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising III-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material.
    Type: Application
    Filed: April 5, 2012
    Publication date: July 26, 2012
    Applicants: COMMISSARIAT A. L'ENERGIE ATOMIQUE, S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, S.A.
    Inventors: Chantal Arena, Laurent Clavelier, Marc Rabarot
  • Publication number: 20120190170
    Abstract: A method for dissolving the buried oxide layer of a SeOI wafer in order to decrease its thickness. The SeOI wafer includes a thin working layer made from one or more semiconductor material(s); a support layer, and a buried oxide (BOX) layer between the working layer and the support layer. The dissolution rate of the buried oxide layer is controlled and set to be below 0.06 ?/sec.
    Type: Application
    Filed: March 1, 2012
    Publication date: July 26, 2012
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventor: Oleg Kononchuk
  • Patent number: 8216916
    Abstract: A method and/or system are provided for producing a structure comprising a thin layer of semiconductor material on a substrate. The method includes creating an area of embrittlement in the thickness of a donor substrate, bonding the donor substrate with a support substrate and detaching the donor substrate at the level of the area of embrittlement to transfer a thin layer of the donor substrate onto the support substrate. The method also includes thermal treatment of this resulting structure to stabilize the bonding interface between the thin layer and the substrate support. The invention also relates to the structures obtained by such a process.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: July 10, 2012
    Assignee: S.O.I. TEC Silicon on Insulator Technologies
    Inventors: Eric Neyret, Sebastien Kerdiles
  • Patent number: 8215401
    Abstract: Apparatus for a drop ball activated device, where a ball seat is concentrically and axially slidably disposed within an outer sleeve having a first internal cylindrical surface, wherein the ball seat comprises at least one radially extending lug, which in a first position extends radially inwards from the internal cylindrical surface, thereby defining a first ball seat diameter less than the diameter of the drop ball. The sleeve comprises at least one groove in its internal surface, and the lug may be received in the groove, thereby defining a second ball seat diameter at least as large as the diameter of the drop ball.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: July 10, 2012
    Assignee: I-Tec AS
    Inventors: Kristoffer Braekke, Geir Lunde, Roger Antonsen
  • Publication number: 20120160515
    Abstract: A valve system for providing fluid flow through radial openings disposed along an axial length of a tubular. The tubular comprises at least one valve group containing at least two valves operable by one drop ball. An inset 302 e.g. of standard grade steel provided in a harder liner 301 in the opening provides an intermediate small opening for at least the time required to open all the remaining valves in the group. The small opening limits the pressure drop over the valve. When all valves are open, the insets 302 are eroded away by an abrasive material, e.g. a slurry used for hydraulic fracturing, and permanent full openings are created.
    Type: Application
    Filed: December 9, 2011
    Publication date: June 28, 2012
    Applicant: I-TEC AS
    Inventors: Kristoffer Braekke, Geir Lunde, Roger Antonsen
  • Publication number: 20120161289
    Abstract: Methods of fabricating semiconductor structures include forming a plurality of openings extending through a semiconductor material and at least partially through a metal material and deforming the metal material to relax a remaining portion of the semiconductor material. The metal material may be deformed exposing the metal material to a temperature sufficient it to alter (i.e., increase) its ductility. The metal material may be formed from one or more of hafnium, zirconium, yttrium and a metallic glass. Another semiconductor material may be deposited over the remaining portions of the semiconductor material, and a portion the metal material may be removed from between each of the remaining portions of the semiconductor material. Semiconductor structures may be formed using such methods.
    Type: Application
    Filed: December 23, 2010
    Publication date: June 28, 2012
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventor: Christiaan J. Werkhoven
  • Publication number: 20120153484
    Abstract: Embodiments of the present invention include methods of directly bonding together semiconductor structures. In some embodiments, a cap layer may be provided at an interface between directly bonded metal features of the semiconductor structures. In some embodiments, impurities are provided within the directly bonded metal features of the semiconductor structures. Bonded semiconductor structures are formed using such methods.
    Type: Application
    Filed: December 16, 2010
    Publication date: June 21, 2012
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventor: Mariam Sadaka
  • Publication number: 20120145382
    Abstract: A valve system for providing fluid flow through radial openings disposed along an axial length of a tubular. The tubular comprises at least one valve group containing at least two valves operable by one drop ball. An inset 302 e.g. of standard grade steel provided in a harder liner 301 in the opening provides an intermediate small opening for at least the time required to open all the remaining valves in the group. The small opening limits the pressure drop over the valve. When all valves are open, the insets 302 are eroded away by an abrasive material, e.g. a slurry used for hydraulic fracturing, and permanent full openings are created.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 14, 2012
    Applicant: I-TEC AS
    Inventors: Kristoffer Braekke, Geir Lunde, Roger Antonsen
  • Patent number: 8178427
    Abstract: The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising III-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: May 15, 2012
    Assignees: Commissariat a. l'Energie Atomique, S.O.I. Tec Silicon on Insulator Technologies, S.A.
    Inventors: Chantal Arena, Laurent Clavelier, Marc Rabarot
  • Publication number: 20120091100
    Abstract: The present disclosure provides a chemical etchant which is capable of removing Ge and Ge-rich SiGe alloys in a controlled manner. The chemical etchant of the present disclosure includes a mixture of a halogen-containing acid, hydrogen peroxide, and water. Water is present in the mixture in an amount of greater than 90% by volume of the entire mixture. The present disclosure also provides a method of making such a chemical etchant. The method includes mixing, in any order, a halogen-containing acid and hydrogen peroxide to provide a halogen-containing acid/hydrogen peroxide mixture, and adding water to the halogen-containing acid/hydrogen peroxide mixture. Also disclosed is a method of etching a Ge or Ge-rich SiGe alloy utilizing the chemical etchant of the present application.
    Type: Application
    Filed: October 14, 2010
    Publication date: April 19, 2012
    Applicants: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Nicolas Daval
  • Publication number: 20120094501
    Abstract: The present invention relates to an etching composition, in particular, for silicon materials, a method for characterizing defects on surfaces of such materials and a process of treating such surfaces with the etching composition, wherein the etching composition comprises an organic oxidant dissolved in a solvent, and a deoxidant, wherein the deoxidant comprises HF or HBF4 or mixtures thereof.
    Type: Application
    Filed: March 8, 2010
    Publication date: April 19, 2012
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Jochen Maehliss, Bernd Kolbesen, Romana Hakim, Francois Brunier
  • Publication number: 20120083100
    Abstract: Methods of depositing material on a substrate include forming a precursor gas and a byproduct from a source gas within a thermalizing gas injector. The byproduct may be reacted with a liquid reagent to form additional precursor gas, which may be injected from the thermalizing gas injector into a reaction chamber. Thermalizing gas injectors for injecting gas into a reaction chamber of a deposition system may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. A pathway may extend from the inlet, through the thermalizing conduit to an interior space within the liquid container, and from the interior space within the liquid container to the outlet. The thermalizing conduit may have a length that is greater than a shortest distance between the inlet and the liquid container. Deposition systems may include one or more such thermalizing gas injectors.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventor: Ronald Thomas Bertram, JR.
  • Publication number: 20120083101
    Abstract: Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to a plurality of gas columns. For example, the substrate may be moved relative to a plurality of substantially aligned gas columns, each disposing a different precursor. Thermalizing gas injectors for generating the precursors may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. Deposition systems for forming one or more III-V semiconductor materials on a surface of the substrate may include one or more such thermalizing gas injectors configured to direct the precursor to the substrate via the plurality of gas columns.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventor: Christiaan J. Werkhoven
  • Patent number: 8148252
    Abstract: Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: April 3, 2012
    Assignee: S.O.I. Tec Silicon on Insulator Technologies
    Inventors: Christophe Figuet, Pierre Tomasini
  • Publication number: 20120074427
    Abstract: The present invention relates to a crack-free monocrystalline nitride layer having the composition AlxGa1-xN, where 0?x?0.3, and a substrate that is likely to generate tensile stress in the nitride layer. The structure successively includes the substrate; a nucleation layer; a monocrystalline intermediate layer having a selected thickness on the nucleation layer; a monocrystalline seed layer of an AIBN compound in which the boron content is between 0 and 10% having a selected thickness on the intermediate layer and a relaxation rate, at ambient temperature, of less than 80%; and the monocrystalline nitride layer.
    Type: Application
    Filed: December 7, 2011
    Publication date: March 29, 2012
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventor: Hacene Lahreche
  • Publication number: 20120061794
    Abstract: Methods of fabricating semiconductor structures include providing a sacrificial material within a via recess, forming a first portion of a through wafer interconnect in the semiconductor structure, and replacing the sacrificial material with conductive material to form a second portion of the through wafer interconnect. Semiconductor structures are formed by such methods. For example, a semiconductor structure may include a sacrificial material within a via recess, and a first portion of a through wafer interconnect that is aligned with the via recess. Semiconductor structures include through wafer interconnects comprising two or more portions having a boundary therebetween.
    Type: Application
    Filed: September 10, 2010
    Publication date: March 15, 2012
    Applicant: S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventor: Mariam Sadaka
  • Patent number: 8133806
    Abstract: Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to a plurality of gas columns. For example, the substrate may be moved relative to a plurality of substantially aligned gas columns, each disposing a different precursor. Thermalizing gas injectors for generating the precursors may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. Deposition systems for forming one or more III-V semiconductor materials on a surface of the substrate may include one or more such thermalizing gas injectors configured to direct the precursor to the substrate via the plurality of gas columns.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: March 13, 2012
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventor: Christiaan J. Werkhoven
  • Patent number: 8114754
    Abstract: Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to the substrate using the glass may be utilized to control a strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the substrate using the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control a strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: February 14, 2012
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventor: Fabrice Letertre
  • Publication number: 20120028440
    Abstract: A method of producing a composite structure comprises a step of producing a first layer of microcomponents on one face of a first substrate, the first substrate being held flush against a holding surface of a first support during production of the microcomponents, and a step of bonding the face of the first substrate comprising the layer of microcomponents onto a second substrate. During the bonding step, the first substrate is held flush against a second support, the holding surface of which has a flatness that is less than or equal to that of the first support used during production of the first layer of microcomponents.
    Type: Application
    Filed: March 4, 2010
    Publication date: February 2, 2012
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Arnaud Castex, Marcel Broekaart
  • Patent number: 8105916
    Abstract: The invention relates to a process for fabricating a heterostructure. This process is noteworthy in that it comprises the following steps: a) a strained crystalline thin film is deposited on, or transferred onto, an intermediate substrate; b) a strain relaxation layer, made of crystalline material capable of being plastically deformed by a heat treatment at a relaxation temperature at which the material constituting the thin film deforms by elastic deformation is deposited on the thin film; c) the thin film and the relaxation layer are transferred onto a substrate; and d) a thermal budget is applied at least the relaxation temperature, so as to cause the plastic deformation of the relaxation layer and the at least partial relaxation of the thin film by elastic deformation, and thus to obtain the final heterostructure.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: January 31, 2012
    Assignee: S.O.I. Tec Silicon on Insulator Technologies
    Inventor: Bruce Faure