Abstract: The disclosed technology relates generally to a magnetic device and more particularly to a spintronic device comprising a tunnel barrier, a hybrid storage layer on the tunnel barrier and a metal layer on the hybrid storage layer. The hybrid storage layer comprises a first magnetic layer, a spacer layer on the first magnetic layer and at least one further magnetic layer on the spacer layer and exchange coupled to the first magnetic layer via the spacer layer.

Abstract: A data processing device for motion segmentation in images obtained by cameras that move in a background environment includes an input for receiving a temporal sequence of images from the cameras and a processor. The processor is adapted for, for at least two images, of the temporal sequence of images, that are obtained by at least two cameras at different points in time, determining epipoles, defining corresponding image regions of limited image disparity due to parallax around the epipoles in the at least two images, and applying a motion segmentation algorithm to the corresponding image regions. Warping is applied to the corresponding image regions to compensate for camera rotation and misalignment beyond a threshold value.

Abstract: A method that provides patterning of an underlying layer to form a first set of trenches and a second set of trenches in the underlying layer is based on a combination of two litho-etch (LE) patterning processes supplemented with a spacer-assisted (SA) technique. The method uses a layer stack comprising three memorization layers: an upper memorization layer allowing first memorizing upper trenches, and then one or more upper blocks; an intermediate memorization layer allowing first memorizing intermediate trenches and one or more first intermediate blocks, and then second intermediate blocks and intermediate lines; and a lower memorization layer allowing first memorizing first lower trenches and one or more first lower blocks, and then second lower trenches and one or more second lower blocks.

Abstract: A solid electrolyte (10) of the present disclosure includes porous silica (11) having a plurality of pores (12) interconnected mutually and an electrolyte (13) coating inner surfaces of the plurality of pores (12). The electrolyte (13) includes 1-ethyl-3-methylimidazolium bis(trifluoromethanesulfonyl)imide represented by EMI-TFSI and a lithium salt dissolved in the EMI-TFSI. A molar ratio of the EMI-TFSI to the porous silica (11) is larger than 1.5 and less than 2.0.

Abstract: A system and method for simulating an electronic circuit is disclosed. The method includes creating a finite set of circuit or device parameter points selected from within an n-dimensional parameter space. The method includes determining, for each circuit or device parameter point of the set, a corresponding response value of the performance metric and a corresponding probability of occurrence. The method includes determining, for a predetermined value of the performance metric, the total probability of occurrence.

Abstract: A method for forming a film of an oxide of In, Ga, and Zn, having a spinel crystalline phase comprises providing a substrate in a chamber; providing a sputtering target in said chamber, the target comprising an oxide of In, Ga, and Zn, wherein: In, Ga, and Zn represent together at least 95 at % of the elements other than oxygen, In represents from 0.6 to 44 at % of In, Ga, and Zn, Ga represents from 22 to 66 at % of In, Ga, and Zn, and Zn represents from 20 to 46 at % of In, Ga, and Zn; and forming a film on the substrate, the substrate being at a temperature of from 125° C. to 250° C., by sputtering the target with a sputtering gas comprising O2, the sputtering being performed at a sputtering power of at least 200 W.

Abstract: A compute cell for in-memory multiplication of a digital data input and a balanced ternary weight, and an in-memory computing device including an array of the compute cells, are provided. In one aspect, the compute cell includes a set of input connectors for receiving modulated input signals representative of a sign and a magnitude of the data input, and a memory unit configured to store the ternary weight. A logic unit connected to the set of input connectors and the memory unit receives the data input and the ternary weight. The logic unit selectively enables one of a plurality of conductive paths for supplying a partial charge to a read bit line during a compound duty cycle of the set of input signals as a function of the respective signs of data input and ternary weight, and disables each of the plurality of conductive paths if at least one of the ternary weight and data input have zero magnitude.

Abstract: Example embodiments relate to image sensors for time delay and integration imaging and methods for imaging using an array of photo-sensitive elements. One example image sensor for time delay and integration imaging includes an array of photo-sensitive elements that includes a plurality of photo-sensitive elements arranged in rows and columns of the array. Each photo-sensitive element includes an active layer configured to generate charges in response to incident light on the active layer. Each photo-sensitive element also includes a charge transport layer. Further, each photo-sensitive element includes at least a first and a second gate, each separated by a dielectric material from the charge transport layer. The array of photo-sensitive elements is configured such that the second gate of a first photo-sensitive element and the first gate of a second photo-sensitive element in a direction along a column of the array are configured to control transfer of charges.

Abstract: A solid nanocomposite electrolyte material comprising a mesoporous dielectric material comprising a plurality of interconnected pores and an electrolyte layer covering inner surfaces of the mesoporous dielectric material. The electrolyte layer comprises: a first layer comprising a first dipolar compound or a first ionic compound, the first dipolar or ionic compound comprising a first pole of a first polarity and a second pole of a second polarity opposite to the first polarity, wherein the first layer is adsorbed on the inner surfaces with the first pole facing the inner surfaces; and a second layer covering the first layer, the second layer comprising a second ionic compound or a salt comprising first ions of the first polarity and second ions of the second polarity, wherein the first ions of the ionic compound or salt are bound to the first layer.

Abstract: A method for three-dimensional imaging of a sample (302) comprises: receiving (102) interference patterns (208) acquired using light-detecting elements (212), wherein each interference pattern (208) is formed by scattered light from the sample (302) and non-scattered light from a light source (206; 306), wherein the interference patterns (208) are acquired using different angles between the sample (302) and the light source (206; 306); performing digital holographic reconstruction applying an iterative algorithm to change a three-dimensional scattering potential of the sample (302) to improve a difference between the received interference patterns (208) and predicted interference patterns based on the three-dimensional scattering potential; wherein the iterative algorithm reduces a sum of a data fidelity term and a non-differentiable regularization term and wherein the iterative algorithm includes a forward-backward splitting method alternating between forward gradient descent (108) on the data fidelity term

Abstract: The present disclosure relates to a fluid analyzing device that includes a sensing device for analyzing a fluid sample. The sensing device includes a microchip configured for sensing the fluid sample, and a closed micro-fluidic component for propagating the fluid sample to the microchip. The fluid sample can be provided to the micro-fluidic component via an inlet of the fluid analyzing device. And a vacuum compartment, which is air-tight connected to the sensing device, can create in the micro-fluidic component a suction force suitable for propagating the fluid sample through the micro-fluidic component.

Abstract: An analog-to-digital converter, ADC, circuitry, comprises: an integrator connected to a capacitor, the integrator being configured to switch between integrating an analog input signal for ramping an integrator output and integrating a reference input signal for returning integrator output towards a threshold; a comparator for comparing integrator output to the threshold; and a timer for determining a time duration during which the reference input signal is integrated, the time duration providing a digital representation of an analog input signal value; the ADC circuitry further comprising a feedforward noise shaping loop configured to store a quantization error signal based on digitizing a first sample, the comparator being configured to receive a feedforward noise shaping signal for changing the threshold for digitizing a later sample of the analog input signal following the first sample.

Abstract: A photonics reservoir computing system is described. The system is configured for propagating at least one optical signal so as to create resulting radiation signals in the output channels. The photonics reservoir computing system further comprises weighting elements for weighting signals from the output channels, and at least one optical detector for optically detecting signals from the output channels. The system is adapted for estimating signals from the output channels through an output of the optical detector.

Abstract: According to an aspect of the present inventive concept there is provided a method for forming a first and a second transistor structure, wherein the first and second transistor structures are spaced apart by an insulating wall, and the method comprising: forming on a semiconductor layer of the substrate a first semiconductor layer stack and a second semiconductor layer stack, each layer stack comprising in a bottom-up direction a sacrificial layer and a channel layer, wherein the layer stacks are spaced apart by a trench extending into the semiconductor layer substrate, the trench being filled with an insulating wall material to form the insulating wall; and processing the layer stacks to form the first and second transistor structures in the first and second device regions, respectively, the processing comprising forming source and drain regions and forming gate stacks; the method further comprising, prior to said processing: by etching removing the sacrificial layer of each layer stack to form a respect

Abstract: According to an aspect of the present inventive concept there is provided a method for manufacturing a fluid sensor device comprising: bonding a silicon-on-insulator arrangement comprising a silicon wafer, a buried oxide, a silicon layer, and a first dielectric layer, to a CMOS arrangement comprising a metallization layer and a planarized dielectric layer, wherein the bonding is performed via the first dielectric layer and the planarized dielectric layer; forming a fin-FET arrangement in the silicon layer, wherein the fin-FET arrangement is configured to function as a fluid sensitive fin-FET arrangement; removing the buried oxide and the silicon wafer; forming a contact to the metallization layer and the fin-FET arrangement, wherein the contact comprises an interconnecting structure configured to interconnect the metallization layer and the fin-FET arrangement; forming a channel comprising an inlet and an outlet, wherein the channel is configured to allow a fluid comprising an analyte to contact the fin-FET a

Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell

Abstract: A device for analysis of cells comprises: an integrated circuit arrangement on a substrate; a dielectric layer formed above the integrated circuit arrangement; a microelectrode array layer formed above the dielectric layer, said microelectrode array layer comprising a plurality of individual electrodes, wherein each electrode is connected to the integrated circuit arrangement through a via in the dielectric layer; and wherein a plurality of longitudinal trenches in the dielectric layer and the microelectrode array layer are for stimulating cell growth on a surface of the device

Abstract: A method for manufacturing an III-nitride semiconductor structure is provided.

Abstract: A method for growing at least one III/V nano-ridge on a silicon substrate in an epitaxial growth chamber. The method comprises: patterning an area on a silicon substrate thereby forming a trench on the silicon substrate; growing the III/V nano-ridge by initiating growth of the III/V nano-ridge in the trench, thereby forming and filling layer of the nano-ridge inside the trench, and by continuing growth out of the trench on top of the filling layer, thereby forming a top part of the nano-ridge, wherein at least one surfactant is added in the chamber when the nano-ridge is growing out of the trench.

Abstract: The present disclosure provides an HBT that includes (i) a semiconductor support layer; at least four wall structures side-by-side on the support layer; (iii) a semiconductor collector-material ridge structure disposed on the support layer between two adjacent wall structures of the at least four wall structures; (iv) a semiconductor base-material layer, wherein a first part of the base-material layer is disposed on a first region of the ridge structure and a second part of the base-material layer is disposed across the wall structures, wherein the base-material layer is supported by the wall structures; (v) a semiconductor emitter-material layer disposed on the first part of the base-material layer; (vi) a base contact layer disposed on the second part of the base-material layer; an emitter contact layer disposed on the emitter-material layer; and (viii) a collector contact layer disposed on a second region of the ridge structure.