Abstract: An apparatus includes a transceiver circuit, an antenna and a focus array. The transceiver circuit may have a plurality of fed channels configured to generate a plurality of signals. The antenna may have a plurality of antenna arrays configured to generate one or more beams in response to the signals. Each antenna array may (i) have a plurality of subarrays and (ii) be coupled to the fed channels of the transceiver circuit. The focus array may have a plurality of focal zones configured to reflect the beams into a beam zone. Each beam may be steerable by the antenna to one of the focal zones at a time. The focal zones may redirect the beams to a plurality of locations within the beam zone.

Abstract: An electronic lock that interacts with a mobile device is presented. In accordance with some embodiments, an electronic lock includes a wireless power receiver configured to receiver power from a mobile device; a processor coupled to receive power from the wireless power receiver; a memory coupled to the processor and to receive power from the wireless power receiver; a communication unit coupled to the processor and to receive power from the wireless power receiver, the communication unit configured to communicate with the mobile device; and an actuator coupled to the processor and to receive power from the wireless power receiver. The processor executes instructions stored in a memory for authenticating the mobile device, and providing signals to the actuator according to instructions received from the mobile device once it is authenticated. The mobile device provides power to the electronic lock and instructs it to lock or unlock a locking mechanism.

Abstract: An apparatus includes a clock tree circuit, a first phase interpolator circuit and a second phase interpolator circuit. The clock tree circuit may be configured to generate a first clock delayed from a system clock by a constant time. The first phase interpolator circuit may be in a calibration loop and configured to generate a second clock with a programmable phase delay relative to the first clock. The programmable phase delay may be controlled by a control value. The calibration loop may be configured to determine the control value that results in a given delay between the system clock and the second clock. The second phase interpolator circuit may be in a normal signal path and configured to generate a third clock with the given delay relative to the first clock using the control value such that the third clock is offset from the system clock by the given delay.

Abstract: A method for encoding a video signal generally includes enabling multiple encoding passes based on a first profile, generating an encoded bitstream during a first time period by encoding each of a plurality of images in the video signal with the multiple encoding passes in a circuit based on the first profile, disabling the multiple encoding passes based on a second profile and generating the encoded bitstream during a second time period by encoding each of the images using a single encoding pass in the circuit based on the second profile. Each profile may determine one or more resources configured to be applied to the images before generating the encoded bitstream.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may generate an output signal with a regulated voltage and maintain a constant switch frequency having a first on time and a first off time. The second circuit may generate a shifted signal based on a phase delay with respect to the output signal and maintain a shifted frequency having a second on time and a second off time. The second on time may follow the first on time by the phase delay. The second on time may be based on the first on time and transient conditions of a load. The apparatus may implement an automatic phase shift adjustment. A current sensing comparison may implement a cycle-by-cycle comparison between the output signal and the shifted signal to determine the second on time and perform a tuning operation to achieve inductor current balancing.

Abstract: An apparatus include a package, a chip and a plurality of bumps. The package may include (i) a plurality of bonding pads configured to exchange a plurality of radio-frequency signals with an antenna panel and (ii) a plurality of transmission lines configured to exchange the radio-frequency signals with the bonding pads. Two of the transmission lines may be connected to each of the bonding pads. The chip may be disposed in the package and may include (i) a plurality of transceiver channels configured to exchange the radio-frequency signals with the transmission lines and (ii) a plurality of switches configured to switch the radio-frequency signals to a signal ground. The bumps may be configured to exchange the radio-frequency signals between the transmission lines of the package and the transceiver channels of the chip. The transmission lines, the bumps and the switches may form a plurality of transmit/receive switches.

Abstract: An apparatus comprising an open loop circuit and a delay circuit. The open loop circuit may be configured to generate an in-phase clock signal by performing a phase alignment in response to (i) a clean version of a system clock and (ii) a delayed version of a strobe signal. The delay circuit may be configured to (i) generate the delayed version of the strobe signal in response to (a) the strobe signal received from a memory interface and (b) a delay amount received from a calibration circuit and (ii) adjust a delay of transferring a data signal through the apparatus in response to (a) the delay amount and (b) the in-phase clock signal. The data signal may be received from the memory interface. The delay of transferring the data signal may be implemented to keep a latency of a data transfer within a pre-defined range.

Abstract: A system for mapping magnetic fields around a transmission coil is presented. The method includes selecting a selected induction loop from an array of selectable induction loops arranged adjacent the transmission coil, detecting current from the selected induction loop, the current being generated by a magnetic field from a transmission coil, to obtain measured values; and comparing measured values with expected values.

Abstract: A register clock driver for a DDR5 memory is presented. A register clock driver (RCD) can include a logic having one or more input channels, each of the one or more input channels receiving input signals; and a plurality of ranked output ports associated with each of the one or more input channels, the logic providing the input signals received on each of the one or more input channels to the associated plurality of ranked output ports according to control signals. The RCD can operate in a default mode, wherein input signals from the input channels are output to both of the output ports associated with that channel, or can operate in a non-default mode where input signals from the input channels are sent to the appropriate ranked output port associated with that channel. In either case, unused signaling on the output ports is held high.

Abstract: An apparatus comprises an amplifier having a predefined linear range and a shunt load. The shunt load may be connected to an output, an input, or between gain stages of the amplifier. An impedance of the shunt load dynamically varies in response to a level of a signal presented at a node formed by interconnection of the shunt load and the amplifier, extending linearity of the amplifier beyond the predefined range.

Abstract: Operation of an Enhanced Data Buffer and Intelligent NV Controller for Simultaneous DRAM and Flash Memory Access has been disclosed. In one implementation a host can operate at full DRAM speed to a DIMM having thereon a NV Controller, DRAM, and flash memory.

Abstract: An apparatus includes an impedance matching network, a first switch circuit, and a second switch circuit. The impedance matching network generally comprises a first port, a second port, and a third port. The first switch circuit may be coupled between the first port and a circuit ground potential. The second switch circuit may be coupled between the second port and the circuit ground potential. The impedance matching network generally provides a first impedance value for the first port and for the third port when the second port is connected to the circuit ground potential. The impedance matching network generally provides a second impedance value for the second port and for the third port when the first port is connected to the circuit ground potential. The first impedance value and the second impedance value are asymmetrical.

Abstract: Methods and apparatuses have been disclosed for a high speed, low power, isolated buffer having architecture and operation that control current flow to minimize coupling and power consumption. Buffer architecture may include one or more of BiCMOS components, an input disabling circuit operated to additionally disable an input circuit when it is also disabled by a selection circuit and a buffer disabling circuit operated to disable the buffer when the input circuit is disabled by the selection circuit. Any one or more of these features may be implemented to improve isolation performance. The selection circuit, input disabling circuit and buffer disabling circuit may be operated by the same control signal.

Abstract: Wide band quadrature signal generation includes a frequency synthesizer generating a LO or 2×LO signal, a polyphase filter coupled to receive the LO signal and generate first in-phase and quadrature LO signals, a 2:1 frequency divider coupled to receive the 2×LO signal and generate second in-phase and quadrature LO signals, and a LO signal selector for selecting either the first or second in-phase LO signals as an output in-phase LO signal and either the first or second quadrature LO signals as an output quadrature LO signal based on an output frequency. In some embodiments, when the output frequency is above a threshold, the first in-phase and quadrature LO signals are selected as the output in-phase and quadrature LO signals and when the output frequency is at or below the threshold, the second in-phase and quadrature LO signals are selected as the output in-phase and quadrature LO signals.

Abstract: Examples of methods and apparatus for performing wavefront parallel decode of video bitstreams are described herein. An example apparatus includes a CABAC decoder configured to decode a CABAC bitstream and generate an output bitstream. The output bitstream contains a plurality of NAL units, each NAL unit being associated with a respective row of a macroblock. The apparatus includes an extractor block configured to extract entry point information associated with a row, and a memory configured to store the extracted entry point information associated with the row. The apparatus includes an insertion block configured to read from the memory the entry point information and insert the entry point information into the NAL unit associated with the row. The plurality of NAL units are provided to at least one macroblock decoder for performing parallel wavefront decode on the output bitstream.

Abstract: An apparatus includes a phased array antenna panel and one or more beam former circuits mounted on the phased antenna array panel. The phased array antenna panel generally comprises a plurality of antenna elements arranged in one or more groups. Each of the one or more beam former circuits may be coupled to a respective group of the antenna elements. Each of the one or more beam former circuits may comprise a plurality of transceiver channels. Each transceiver channel generally comprises a power amplifier circuit configured, when operating in a transmit mode, to drive a respective one of the antenna elements. The power amplifier generally comprises a feedback network coupled between an output and an input of the power amplifier circuit.

Abstract: An e-band transceiver includes a transmitter circuit and a receiver circuit. The transmitter circuit includes a surface mounted technology (SMT) module on which is mounted a silicon-germanium (SiGe) bipolar plus CMOS (BiCMOS) converter, a gallium arsenide (GaAs) pseudomorphic high-electron-mobility transistor (pHEMT) output amplifier coupled to the SiGe BiCMOS converter, and a microstrip/waveguide interface coupled to the GaAs pHEMT output amplifier. The receiver circuit of the e-band transceiver includes a receiver-side SMT module on which is mounted a receiver-side SiGe BiCMOS converter, a GaAs pHEMT low noise amplifier coupled to the receiver-side SiGe BiCMOS converter, and a receiver-side microstrip/waveguide interface coupled to the receiver-side GaAs pHEMT low noise amplifier.

Abstract: A time-to-digital converter (TDC, 110) obtains a Start signal to indicate the start of an event, and a Stop signal whose assertion indicates the stop of the event. The Stop signal can be asserted multiple times due to false indications of the event stop. The TDC continuously monitors the Stop signal to generate a separate digital value (T.j_i) for the duration from the event's starting time to each assertion of the Stop signal. The digital values can be analyzed to select the true duration of the event. Other features and embodiments are also provided.

Abstract: Methods of estimating frequency skew in a packet network include determining a representation of a packet delay variation (PDV) sequence from an initial estimate of frequency skew between master and slave devices in the packet network and timestamps transmitted therebetween. An operation is performed to extract a statistical mode from an empirical probability distribution function (PDF) of the representation of the PDV sequence, where the statistical mode corresponds to a value at which the PDF has its maximum value. The, an updated estimate of the frequency skew is generated by determining a slope between timestamps at indices associated with a plurality of points in the representation of the PDV sequence that are within a range of the statistical mode.

Abstract: A method and apparatus for a novel adaptive equalization technique for a Serializer/Deserializer receiver is disclosed. In one approach, adjustment of AC and DC gains is performed before DFE coefficients are adjusted. Further after the equalization an electrical idle threshold may be set based on the results of the equalization.