Patents Assigned to Integrated Device Technology, Inc.
  • Compensation of deterministic crosstalk in memory system
    Patent number: 10311926
    Abstract: An apparatus includes a detector circuit and a receiver circuit. The detector circuit may be configured to generate a control signal indicating a start of a plurality of strobe edges in a strobe signal. The receiver circuit may be configured to initialize an equalizer circuit in response to the control signal. The equalizer circuit may be configured to compensate a data signal for crosstalk coupled from the strobe edges to the data signal.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: June 4, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: Craig DeSimone
  • Long range beamforming and steering in wireless communication links
    Patent number: 10306484
    Abstract: An apparatus includes a transceiver circuit, an antenna and a focus array. The transceiver circuit may have a plurality of fed channels configured to generate a plurality of signals. The antenna may have a plurality of antenna arrays configured to generate one or more beams in response to the signals. Each antenna array may (i) have a plurality of subarrays and (ii) be coupled to the fed channels of the transceiver circuit. The focus array may have a plurality of focal zones configured to reflect the beams into a beam zone. Each beam may be steerable by the antenna to one of the focal zones at a time. The focal zones may redirect the beams to a plurality of locations within the beam zone.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: May 28, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Mohammad S. Akhter, John Bradley Deforge
  • High signal voltage tolerance in single-ended memory interface
    Patent number: 10304520
    Abstract: An apparatus includes a line-termination circuit and a continuous-time linear equalizer circuit. The line-termination circuit may be configured to generate a data signal in response to an input signal. The input signal generally resides in a first voltage domain. The input signal may be single-ended. The data signal may be generated in the first voltage domain. The continuous-time linear equalizer circuit may be configured to generate an intermediate signal by equalizing the data signal relative to a reference voltage. The continuous-time linear equalizer circuit generally operates in a second voltage domain. The first voltage domain may be higher than the second voltage domain.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: May 28, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Yi Xie, Yue Yu
  • Scalable Coherent Apparatus and Method
    Publication number: 20190155738
    Abstract: Scalable Coherent Apparatus and Method have been disclosed. In one implementation a dual directory approach is used to implement scalable coherent accesses in a heterogeneous system.
    Type: Application
    Filed: January 29, 2019
    Publication date: May 23, 2019
    Applicant: Integrated Device Technology, Inc.
    Inventor: Mohammad Shahanshah Akhter
  • Wireless power transmitter
    Patent number: 10284015
    Abstract: A wireless power transmission system is presented. In some embodiments, a transmission unit includes a first inductor with a center tap, a first end tap, and a second end tap; a pre-regulator coupled to provide current to the center tap; a switching circuit coupled to the first end tap and the second end tap, the switching circuit alternately coupling the first end tap and the second end tap to ground at a frequency; and a resonant circuit magnetically coupled to the first inductor, the resonant circuit wirelessly transmitting power. In some embodiments, the switching circuit can be formed of FETs. The current provided to the center tap can be controlled in response to current sensors.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: May 7, 2019
    Assignee: Integrated Device Technology, Inc.
    Inventor: Mehmet K. Nalbant
  • Rate-distortion optimizers and optimization techniques including joint optimization of multiple color components
    Patent number: 10277907
    Abstract: Examples of encoders and video encoding are described that include optimizers and techniques for optimizing syntax elements such as transform coefficients. In some examples, multiple color components of a video signal may be jointly optimized by employing a cost calculation using a combination of distortion and/or rate metrics for multiple color components. In some examples, a color transformation may occur and the optimization may take place in a different color domain than encoding. In some examples, distortion metrics used in the cost calculations performed by optimizers are based on structural similarity index.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: April 30, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Krzysztof Hebel, Alexandros Tourapis
  • Wirelessly synchronized clock networks
    Patent number: 10264542
    Abstract: An apparatus includes a first independently clocked device and one or more second independently clocked devices. The first independently clocked device may comprise a clock generator. The clock generator may be configured to generate a clock signal. The first independently clocked device may be configured to wirelessly broadcast a synchronization signal based on the clock signal. The one or more second independently clocked devices may each comprise respective clock generators. The one or more second independently clocked devices may (a) be configured to receive the synchronization signal from the first independently clocked device and (b) synchronize the respective clock generators to the clock signal of the first independently clocked device in response to the synchronization signal.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: April 16, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Jagdeep Bal, Elie Ayache, Eduard Van Keulen
  • Entropy encoding initialization for a block dependent upon an unencoded block
    Patent number: 10264261
    Abstract: Apparatuses and methods for initializing a CABAC state are disclosed herein. An example apparatus may include an encoder configured to receive a macroblock dependent on at least one unencoded macroblock. The encoder may further be configured to receive a plurality of CABAC states and initialize CABAC in accordance with one of the plurality of CABAC states to encode the macroblock prior to the at least one unencoded macroblock being encoded.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: April 16, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Eric C. Pearson, Pavel Novotny
  • Separate clock synchronous architecture
    Patent number: 10261539
    Abstract: An apparatus includes a plurality of independently clocked devices and a low frequency beacon. Each of the plurality of independently clocked devices has a respective local clock generator. The low frequency beacon communicates a low frequency synchronization signal to each of the independently clocked devices. The respective local clock generators of the plurality of independently clocked devices are generally synchronized using the low frequency synchronization signal.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: April 16, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Jagdeep Bal, Ron Wade
  • Arbitrary delay buffer
    Patent number: 10250242
    Abstract: A signal may be arbitrarily delayed in discrete steps by an arbitrary delay buffer having an analog delay and a digital delay. An analog delay may have a number of selectable delay stages (e.g. ring oscillator with VCDL stages). A digital delay may have rising and falling edge detectors, resettable ring oscillators that oscillate in response to rising or falling edges and counters to count oscillations and generate rising and falling edge delay signals when oscillation counts reach rising and falling edge delay counts. A resettable ring oscillator may have a resettable stage (e.g. VCDL) that may be enabled and disabled. Selection of one or both digital and analog delays and respective delay times may be based on one or more characteristics. For example, an analog delay may delay an input signal or a delayed input signal received from the digital delay based on input signal frequency or total delay.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: April 2, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: Chengming He
  • Resynchronization of a clock associated with each data bit in a double data rate memory system
    Patent number: 10241538
    Abstract: An apparatus comprising an input interface, an output interface and an adjustment circuit. The input interface may comprise a plurality of input stages each configured to receive a data signal and a clock signal and present an intermediate signal. The output interface may comprise a plurality of output stages each configured to receive the intermediate signal, receive an adjusted clock signal and present an output signal. The adjustment circuit may comprise a plurality of adjustment components each configured to (i) receive the clock signal and (ii) present the adjusted clock signal. The clock signal may be presented through a clock tree. The adjustment circuit may be located near the output interface. The adjustment circuit may be configured to resynchronize the clock signal for each bit transmitted to reduce a mismatch between a bit to bit delay and a delay caused by the clock tree.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: March 26, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: David Chang, Xudong Shi, Shubing Zhai, Chenxiao Ren
  • Signal driver slew rate control
    Patent number: 10236870
    Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a plurality of delayed signals each as a copy of an input signal shifted in time by a sequence of respective delays based on a control signal. At least two of the respective delays may have a different duration. The first circuit may also be configured to change a number of driver signals that are active during each delay in the sequence of respective delays based on the input signal and the plurality of delayed signals to control a slew rate of an output signal. The second circuit may be configured to drive the output signal in response to the driver signals.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: March 19, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Zhigang Hu, Hui Yu, Shaokang Wang, Yuan Zhang, Yue Yu
  • Scalable coherent apparatus and method
    Patent number: 10235295
    Abstract: Scalable Coherent Apparatus and Method have been disclosed. In one implementation a dual directory approach is used to implement scalable coherent accesses in a heterogeneous system. A transaction identification mapping for coherent RapidIO memory transactions between a plurality of external hardware processing elements is used. Source transaction identification encoding is a combination of bits from two advanced extensible interface identifications. Target transaction identification is decoded into a combination of bits for two advanced extensible interface identifications.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: March 19, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: Mohammad Shahanshah Akhter
  • Apparatuses and methods for optimizing rate-distortion of syntax elements
    Patent number: 10230956
    Abstract: Methods and apparatuses for optimizing rate-distortion of syntax elements are disclosed herein. An optimization block may be used in a video encoder and may include a candidate generation block and a best cost block. The optimization block may be configured to generate a plurality of candidates corresponding to respective differential levels. Each of the plurality of candidates may be based, at least in part, on a DC coefficient and provide a respective rate-distortion cost. The best cost block may be coupled to the candidate generation block and may be configured to select a candidate of the plurality of candidates according to a criteria.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: March 12, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Krzysztof Hebel, Eric C. Pearson, Pavel Novotny
  • Method and apparatus for flexible coherent and scale-out computing architecture
    Patent number: 10230476
    Abstract: A Method and Apparatus for Flexible Coherent and Scale-out Computing Architecture have been disclosed. In one implementation a plurality of integrated photonics are used to effect communications.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: March 12, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: Mohammad Shahanshah Akhter
  • Wireless power transmitter having low noise and high efficiency, and related methods
    Patent number: 10211720
    Abstract: A wireless power transmitter comprises a bridge inverter including a first switch and a second switch coupled together with a first switching node therebetween, and a first capacitor coupled to the first switching node. The transmitter further includes control logic configured to control the first switch and the second switch according to an operating frequency to generate an AC power signal from a DC power signal, and a resonant tank operably coupled to the first switching node of the bridge inverter, the resonant tank configured to receive the AC power signal and generate an electromagnetic field responsive thereto. A method for operating the wireless power transmitter and a method for making the wireless power transmitter are also disclosed.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: February 19, 2019
    Assignee: Integrated Device Technology, Inc.
    Inventor: Mehmet K. Nalbant
  • Fast-response hybrid lock detector
    Patent number: 10211843
    Abstract: An apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to (i) receive pulses generated in response to a comparison of a feedback signal and a reference signal, (ii) filter the pulses when a frequency of the feedback signal is close to a frequency of the reference signal and (iii) generate an enable signal in response to the filtered pulses. The digital circuit may be configured to generate an output signal representing a lock status between (i) the feedback signal and (ii) the reference signal. The lock status may be determined (a) during a decision window based on a number of pulses of the reference signal and (b) when the enable signal is active (B) the decision window may be repeated periodically until the enable signal is not active.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: February 19, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Xinqing Chen, HaiQi Liu, Yuan Zhang
  • System and method for wireless power transfer using over-voltage protection
    Patent number: 10199818
    Abstract: A system and method of over-voltage protection includes a switch coupled between a power source and a load, a detection circuit configured to detect an onset of an over-voltage event at the load; and a driver circuit coupled to the switch and the detection circuit. The driver circuit includes a boost sub-circuit that provides a low-resistance path for opening the switch in a boost mode, the boost mode being triggered by the onset of the over-voltage event and having a predetermined duration and a steady state sub-circuit that provides a high-resistance path for holding the switch open during steady state operation when the boost mode.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: February 5, 2019
    Assignee: Integrated Device Technology, Inc.
    Inventors: Rosario Pagano, Herman R. Paz, Siamak Abedinpour
  • Auto-phase-shifting and dynamic on time control current balancing multi-phase constant on time buck converter
    Patent number: 10200050
    Abstract: An apparatus including a first circuit and a second circuit. The first circuit may generate an output signal with a regulated voltage and maintain a constant switch frequency having a first on time and a first off time. The second circuit may generate a shifted signal based on a phase delay with respect to the output signal and maintain a shifted frequency having a second on time and a second off time. The second on time may follow the first on time by the phase delay. The second on time may be based on the first on time and transient conditions of a load. The apparatus may implement an automatic phase shift adjustment. A current sensing comparison may implement a cycle-by-cycle comparison between the output signal and the shifted signal to determine the second on time and perform a tuning operation to achieve inductor current balancing.
    Type: Grant
    Filed: February 24, 2018
    Date of Patent: February 5, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: Chenxiao Ren
  • High efficiency wireless power system
    Patent number: 10199865
    Abstract: In accordance with some embodiments, a transmitter for wireless transfer includes a rectifier that receives an AC voltage and provides a DC voltage; a capacitor that receives and smooths the DC voltage; a regulator that receives the DC voltage and outputs an input voltage; and a wireless transmitter that receives the input voltage and transmits wireless power.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: February 5, 2019
    Assignee: Integrated Device Technology, Inc.
    Inventor: Mehmet K. Nalbant