Patents Assigned to Integrated Device Technology, Inc.
  • Patent number: 10367494
    Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a waveform in response to a frequency of an input clock signal and a threshold frequency. The second circuit may be configured to generate a control signal in response to a type of the waveform. The type of the waveform may comprise at least one of pulses and a steady state. The control signal may have a first state when the type of the waveform is the pulses and a second state when the type of the waveform is the steady state. A width of the pulses may be based on the threshold frequency.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: July 30, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Xinqing Chen, HaiQi Liu, Yuan Zhang
  • Patent number: 10360485
    Abstract: According to another embodiment, a system includes a driver circuit that drives a first output and a second output; a coil coupled between the first output and the second output such that the driver circuit drives current through the coil in response to control signals; and a programmable slew circuit coupled to the driver circuit. In some embodiments, a switch is coupled between the first output and the coil. In some embodiments an over-voltage protection circuit is coupled to protect the driver circuit.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: July 23, 2019
    Assignee: Integrated Device Technology, Inc.
    Inventors: Rui Liu, Tao Qi, Lijie Zhao, Gustavo James Mehas, Tae Kwang Park, Zhitong Guo, Siqiang Fan
  • Patent number: 10360970
    Abstract: An apparatus includes a plurality of termination points and a clock mesh network. The termination points may be configured to send/receive timing signals. Each of the termination points may comprise an inductor. The clock mesh network may be configured to provide a path to transmit the timing signals from a clock source to a plurality of components and implement a condition using the inductors. The inductors for each of the termination points may be implemented to meet the condition. Values for the inductors may be determined based on characteristics of the clock mesh network. The condition may prevent power loss.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: July 23, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: David Chang
  • Patent number: 10355525
    Abstract: An inductive wireless power transfer device comprises a transmitter that comprises a transmit coil configured to generate a wireless power signal to a coupling region in response to an input voltage, and a modulator configured to modulate the wireless power signal and encode data with the wireless power signal to establish a back-channel communication link from the transmitter to a receiver. An inductive wireless power receiving device comprises a receiver that comprises a receive coil configured to generate a time varying signal in response to receiving a modulated wireless power signal from a transmitter in a coupling region, and a demodulator configured to demodulate the modulated wireless power signal from an established back-channel communication link from the transmitter to a receiver. Related inductive wireless power transfer systems and methods for back-channel communication from the transmitter to the receiver of an inductive wireless power transfer system are disclosed.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 16, 2019
    Assignee: Integrated Device Technology, Inc.
    Inventors: Manjit Singh, Siamak Bastami, David Wilson
  • Patent number: 10355699
    Abstract: An apparatus comprising an accumulator circuit and an offset register. The accumulator circuit may be configured to (a) receive a plurality of frequency offset values from a plurality of sourcing DPLLs and (b) generate a current combined offset value in response to a sum of the frequency offset values. The offset register may be configured to (a) store an offset value corresponding to the current combined offset value in a first mode and (b) store an offset value corresponding to an updated offset value in a second mode. The updated offset value may comprise a difference between the offset value stored in the offset register and the current combined offset value. The offset value may be presented to a receiving DPLL during a re-arrangement of the sourcing DPLLs. Presenting the offset value may reduce a phase transient caused by the re-arrangement.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: July 16, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: Menno Spijker
  • Patent number: 10356405
    Abstract: A video encoding method for encoding a stream of baseband video data. The stream of baseband video data is received as a plurality of coding units. Statistics of each coding unit in the plurality of coding units are gathered. A quantization parameter (QP) for each coding unit is determined from the corresponding statistics. The coding unit is trial encoded using the QP to generate a trial encoded coding unit; and the QP is updated based on the trial encoded coding unit. Trial encoding the coding unit and updating the QP are repeated until the trial encoded coding unit meets a predetermined criterion. Then the coding unit is final encoded using the updated QP to generate a final encoded coding unit.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: July 16, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Pavel Novotny, Eric C. Pearson
  • Publication number: 20190212445
    Abstract: A laser distance sensor (LDS) performs multiple measurement attempts with different values of operating parameters, e.g. of laser power gain (GL) or received light amplifier gain (GTIA). The parameter values, and the order of values for different measurement attempts, are determined from analysis of prior measurement data. Such data may include parameter values used in prior satisfactory measurements. The parameter values, the order indication, and other measurement information are stored by the LDS for use in subsequent measurements. Machine learning is performed to analyze stored data and determine the best parameter values and order for the current measurement.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 11, 2019
    Applicant: Integrated Device Technology, Inc.
    Inventor: Cheng Wen HSIAO
  • Patent number: 10341673
    Abstract: Examples of systems, apparatuses, and methods for to transcoding a bitstream are described herein. An example content distribution system may include an interconnect configured to provide encoded video data from an encoder to a decoder. The interconnect is configured to receive a bitstream including the encoded video data from the encoder. The bitstream is encoded using a first lossless coding methodology. The interconnect including a transcoder configured to transcode the bitstream using a second lossless coding methodology to provide a transcoded bitstream.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: July 2, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: Eric C. Pearson
  • Patent number: 10340786
    Abstract: A rectifier circuit can include a plurality of FETs arranged as a rectifier; and a start-up circuit applied to each of the plurality of FETs that turn each of the FETs off during a circuit startup period, wherein the start-up circuit provides a large impedance for low power dissipation during normal operation of the rectifier.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: July 2, 2019
    Assignee: Integrated Device Technology, Inc.
    Inventors: Lijie Zhao, Yue Wang, Stephen Ulbrich
  • Publication number: 20190187628
    Abstract: A multi-stop time-to-digital converter (TDC, 110) includes single-stop TDCs (326, 510) connected to output nodes of a ring oscillator (504). Other features and embodiments are also provided.
    Type: Application
    Filed: December 20, 2017
    Publication date: June 20, 2019
    Applicant: Integrated Device Technology, Inc.
    Inventor: Min CHU
  • Patent number: 10325637
    Abstract: An apparatus includes a plurality of memory devices and a control circuit. The control circuit may be configured to enable a plurality of access modes for the plurality of memory devices. In a one-channel mode, all of the memory devices are accessed using a single selectable channel. In a two-channel mode, a first portion of the plurality of memory devices is accessed using a first channel and a second portion of the plurality of memory devices is accessed using a second channel.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: June 18, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: Alejandro F. Gonzalez
  • Patent number: 10320381
    Abstract: Sequenced switching mitigates impedance variations and signal reflections during switching events by stepping a switch incrementally through a sequence of different states from a start state to at least one intermediate state to an end state. Various architectures, sequencing and step control techniques may permit any degree of mitigation, including to the point of essentially eliminating impedance glitches. Sequential reconfiguration of the structure and/or parameters of one or more switch branches may permit simplification of related programming and circuitry while increasing the lifespan of components spared from unmitigated current and voltage spikes. Each switch branch being transitioned during a switch event may sequence differently than other branches based on the start state, end state and configuration of each branch.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: June 11, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Kathiravan Krishnamurthi, Jean-Marc Mourant, Olivier Hubert, Shawn Bawell
  • Patent number: 10320376
    Abstract: A frequency divider system and method includes a split-divisor frequency divider module. The split-divisor frequency divider module receives a clock signal and generates an output signal based on a first divisor and a second divisor. The clock signal and output signal each have rectangular waveforms characterized by a respective frequency and pulse width. The frequency of the output signal is a selectable integer fraction of the frequency of the clock signal, the frequency of the output signal being selected based on a sum of the first and second divisors. The pulse width of the output signal is a selectable integer number of clock cycles, the pulse width of the output signal being selected based on at least one of the first divisor and the second divisor.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: June 11, 2019
    Assignee: Integrated Device Technology, Inc.
    Inventor: Richard Geiss
  • Patent number: 10320234
    Abstract: A wireless power receiver comprises a resonant tank configured to generate an AC power signal responsive to an electromagnetic field, a rectifier configured to receive the AC power signal and generate a DC output power signal, and control logic configured to control the resonant tank to reconfigure and adjust its resonant frequency responsive to a determined transmitter type of a wireless power transmitter. The control logic may operate the wireless power receiver as a multimode receiver having a first mode for a first transmitter type and a second mode for a second transmitter type. The resonant tank may exhibit a different resonant frequency for each of the first mode and the second mode. A method comprises determining a transmitter type for a wireless power transmitter desired to establish a mutual inductance relationship, and adjusting a resonant frequency of a resonant tank of a wireless power receiver.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: June 11, 2019
    Assignee: Integrated Device Technology, Inc.
    Inventor: Ovidiu Aioanei
  • Publication number: 20190170584
    Abstract: Embodiments of the invention relate to a method for producing a color sensor with a sensor characteristic adjusted by three sensor elements that each comprise an element characteristic, and a color filter cooperating with the sensor elements and consisting of color filter elements that each comprise a filter element characteristic, and to a color sensor. Embodiments include a method with which a color sensor with a precisely adjustable sensor characteristic can be produced from several photosensitive elements and from simple filter elements is solved in that the particular filter element characteristics are adjusted in such a manner that they have in cooperation with the respective element characteristic an interim characteristic of the sensor which deviates from the sensor characteristic on the whole, wherein the sensor characteristic is generated from the interim characteristic by a transformation algorithm using transformation parameters.
    Type: Application
    Filed: July 4, 2017
    Publication date: June 6, 2019
    Applicant: Integrated Device Technology, Inc.
    Inventors: Matthias GARZAROLLI, Thomas REICHEL
  • Patent number: 10313565
    Abstract: A technique to perform edge-aware spatial noise filtering that may filter random noise from frames while maintaining the edges in the frames. The technique may include receiving a frame comprising a pint ht of pixels, filtering a subset of the plurality of pixels based on a weighting factor associated with each pixel of the subset of pixels, wherein the weighting factor is at least in part based on a difference in pixel value between the pixel and the individual pixels in the subset, and providing the filtered pixel to an encoder for encoding. Example implementation may include a spatial noise filter to receive an image, the noise level, and configuration parameters, and configured to determine weighting factors of pixels of the image based on differences in pixel values and a set of configuration parameters, and further configured to filter noise from the image based on the weighting factors of the pixels.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: June 4, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Pavel Novotny, Eric Pearson
  • Patent number: 10312736
    Abstract: A wireless power transmission system is presented. In some embodiments, a transmission unit includes a first inductor with a center tap, a first end tap, and a second end tap; a pre-regulator coupled to provide current to the center tap; a switching circuit coupled to the first end tap and the second end tap, the switching circuit alternately coupling the first end tap and the second end tap to ground at a frequency; and a resonant circuit magnetically coupled to the first inductor, the resonant circuit wirelessly transmitting power. In some embodiments, the switching circuit can be formed of FETs. The current provided to the center tap can be controlled in response to current sensors.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: June 4, 2019
    Assignee: Integrated Device Technology, Inc.
    Inventor: Mehmet K. Nalbant
  • Patent number: 10312961
    Abstract: An apparatus comprises an input port, an output port, and a resonant receive switch circuit. The resonant receive switch circuit may be coupled between the input port and the output port. The resonant receive switch circuit may comprise a switch and an input matching circuit. When the switch is in a non-conducting state, a signal at the input port is passed to the output port. When the switch is in a conducting state, the signal at the input port is prevented from reaching the output port.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: June 4, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Victor Korol, Roberto Aparicio Joo, Naveen Krishna Yanduru
  • Patent number: 10313470
    Abstract: A system includes at least one end-node, at least one edge node, and an edge cloud video headend. The at least one end node generally implements a first stage of a multi-stage hierarchical analytics and caching technique. The at least one edge node generally implements a second stage of the multi-stage hierarchical analytics and caching technique. The edge cloud video headend generally implements a third stage of the multi-stage hierarchical analytics and caching technique.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: June 4, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: Mohammad S. Akhter
  • Patent number: 10311940
    Abstract: An apparatus includes a receiver circuit and a data buffer. The receiver circuit may comprise a decision feedback equalizer (DFE). The data buffer circuit may be configured to initialize a condition of the receiver circuit in response to a control signal prior to reception of a command sequence associated with a directed access to a memory system. The control signal generally indicates detection of a non-consecutive clock associated with a start of the command sequence. The data buffer circuit may generate one or more tap enable signals configured to determine a number of clock cycles during which a contribution of one or more taps of the decision feedback equalizer (DFE) are delayed.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: June 4, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Craig DeSimone, Praveen Singh