Abstract: A database stores information about known hosts, the applications or services they host, and the ports (known as confirmed ports) used by the applications/services. A static traffic analyzer analyzes traffic data and identifies packets communicating with (either sent to or received from) confirmed ports on hosts. A dynamic traffic analyzer analyzes the traffic data and identifies packets communicating with unconfirmed ports on hosts. A host identifier uses the resulting static and dynamic traffic to identify hosts for which firewall rules should be generated.

Abstract: Methods and designs for increasing interconnect areas for interconnect bumps are disclosed. An interconnect bump may be formed on a substrate such that the interconnect bump extends beyond a contact pad onto a substrate. An interconnect bump may be formed on a larger contact pad, the bump having a large diameter.

Abstract: Methods and devices for networked applications are disclosed. In one embodiment, a device instructs a proxy server to receive traffic inbound for the device, and to notify the device when such traffic arrives. The device can then sleep, except for a notification channel that listens for a wakeup message from the proxy server. The proxy server detects traffic inbound for proxied devices, caches the data from that traffic, and issues notification messages to the proxied devices to cause those devices to download the cached data. One use for such a system is in instant messaging, as it allows a subscriber to place a battery-powered computing device in sleep mode while still advertising a continuous presence to her messaging buddies.

Abstract: A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue.

Abstract: The invention comprises an apparatus and method of prefetching from a memory device having interleaved channels. The chipset prefetcher comprises a stride detector to detect a stride in a stream, a prefetch injector to insert prefetches onto the memory device, a channel mapper to map the prefetches to each channel of the memory device, a scheduler to schedule the prefetches onto the memory device in a DRAM-state aware manner, a throttling heuristic to scale the number of prefetches, and a prefetch data buffer to store prefetch data. The method of prefetching comprises tracking the state of streams, detecting a stride on one of the streams, selecting the stream with the stride for prefetch injection, enqueueing prefetches from the selected stream, mapping the prefetches to each of the interleaved channels, injecting the prefetches from the selected stream into each of the interleaved channels, and scheduling the prefetches onto the memory device in a DRAM-state aware manner.

Abstract: One disclosed method includes controlling an output voltage to track a reference voltage by using a feedback loop to monitor an output duty cycle and to maintain an output voltage that is substantially constant relative to the reference voltage.

Abstract: Embodiments of the invention may provide a method to send a packet from an endpoint in an advanced switching fabric and starting a timer to run until receiving a response packet or receiving an event packet notifying of a device failure, save a copy of the sent packet, detect if the timer has expired, retransmit the packet after the timer has expired and resetting the timer; and run a faulty device detection algorithm if the packet has been retransmitted a predetermined number of times. Furthermore, some embodiments may provide an apparatus with a retransmit buffer, and an endpoint that can send a packet and save a copy of the packet in the retransmit buffer, detect if a timer expired and retransmit the packet after the timer has expired and no packet was received in response to the transmitted packet, and run a faulty device detection algorithm.

Abstract: An embodiment of the present invention may comprise a method to calculate current bandwidth usage by existing connections in a switching fabric between endpoints in a device, calculate available bandwidth for a new connection, and select a path from the multiple paths based on the bandwidth calculations. Some embodiments may be a device, comprising a port to connect the device to paths in an advanced switching fabric, a module to determine current bandwidth usage on the paths, calculate a cumulative bandwidth usage on the paths, calculate available bandwidth for a new connection, and select one of multiple paths available for the new connection.

Abstract: Systems and methods are disclosed for measuring signals on an integrated circuit die. In one embodiment, a reference signal is distributed to die locations proximal to the signals to be measured. The reference signal is transmitted over transport paths coupling each of the signals to be measured to the die output. The signals to be measured are transmitted over their respective transport paths and measured at the die output. The relative delay between the signals can be calculated using the reference signal measurements.

Abstract: One disclosed system includes a plurality of current sink elements coupled between a power supply and a reference potential. A plurality of multiplexers are configured to enable the current sink elements to sink current, and a plurality of selection inputs are configured to control the state of the multiplexers.

Abstract: A single copy memory sharing scheme between multiple endpoints in an interconnect architecture may use a buffer management method in an advanced switching fabric having multiple endpoints that divides a simple load and store memory aperture into a buffer descriptor and at least one data buffer, provides offset addressing in the buffer descriptor, and accesses the buffer descriptor by more than one endpoint to allow direct memory access with multiple endpoints in a simple load and store memory aperture. An apparatus may have a memory, and a device associated with the memory, the device to divide the memory into a buffer descriptor and at least one data buffer, and to store offset address information in the buffer descriptor such that another device can access a data buffer in the memory.

Abstract: Systems and methods employing a flexible mesh structure for hierarchical scheduling are disclosed. The method generally includes reading a packet grouping configured in a two dimensional mesh structure of N columns, each containing M packets, selecting and promoting a column best packet from each column to a final row containing N packets, reading, selecting and promoting a final best packet from the final row to a next level in the hierarchy. Each time a final best packet is selected and promoted, the mesh structure can be refreshed by replacing the packet corresponding to the final best packet, and reading, selecting and promoting a column best packet from the column containing the replacement packet to the final row. As only the column containing the replacement packet and the final row are read and compared for each refresh, the mesh structure results in reduced read and compare cycles for schedule determination.

Abstract: Some embodiments of the invention enable debugging functionality for memory devices residing on a memory module that are buffered from the memory bus by a buffer chip. Some embodiments map connector signals from a tester coupled to the high speed interface between the buffer chip and the memory bus to an interface between the buffer chip and the memory devices. During test mode, some embodiments bypass the normal operational circuitry of the buffer chip and provide a direct connection to the memory devices. Other embodiments use the existing architecture of the buffer chip to convert high speed pins into low speed pins and map them to pins that are connected to the memory devices. Other embodiments are described in the claims.

Abstract: A mechanism detects multiple assertions in a bus efficiently by encoding each of N bus lines with log2(N) pairs of bit lines.

Abstract: Systems and methods using network interface card-based (NIC-based) prefetching for host TCP context lookup are disclosed. The process generally includes hashing, by the NIC, a packet received over the network, computing a host hash table cache line in a host memory using the hash value and using a hash table pages table containing host memory physical page addresses of a host hash table, and computing a host context table cache line in a host memory using the hash value and using a context table pages table containing host memory physical page addresses of a host context table. The NIC may be initialized with the hash table pages table and the context table pages table as well as with the a set number of hash node entries in the hash table of the host memory.

Abstract: Ethernet systems and methods for auto-learning of MAC addresses and lexicographic lookup of hardware databases are disclosed. An Ethernet network device generally includes a hardware MAC address database containing MAC address entries and a hardware MAC address learning engine in communication with the hardware MAC address database and configured to receive an unresolved source MAC address to be learned and to record the unresolved source MAC address in the hardware MAC address database in a corresponding MAC address entry. The Ethernet network device may also include a hardware lexicographic lookup engine configured to perform hardware lookups of MAC address entries in the hardware MAC address database and to interface with a management application program interface (API) for management of the Ethernet network device.

Abstract: Systems and methods are disclosed for aligning data in memory access and other applications. In one embodiment, a group of data is obtained for storage in a memory unit. The memory unit has two banks. If the data is aligned, a first portion of the data is written to the first memory bank and a second portion is written to the second memory bank. If the data is not aligned, the first portion is written to the second memory bank and the second portion is written to the first memory bank. In one embodiment, the data is written to the first and second memory banks in a substantially simultaneous manner.

Abstract: Systems and methods are disclosed for managing congestion in a system or network fabric using a time-stamp. In one embodiment, a time-stamp is applied to packets at a first node. The packets are then transmitted to a second node. When a packet reaches the second node, the packet's time-stamp is used to calculate the amount of time taken for the packet to reach the second node. If this amount of time is greater than a predefined amount, a notification is sent to the first node. In response to receiving the notification, the first node reduces the rate at which at least some additional packets are transmitted to the second node.

Abstract: A common mode ramp voltage generator may be used in generating a ramp voltage for the amplifier and thereby eliminating or reducing pop noise.

Abstract: Use of data poisoning techniques may permit proactive operating system recovery without needing to always bringing down the operating system when uncorrectable errors are encountered.