Abstract: A compressed switch data storage for a network system is disclosed. The system includes a plurality of network channels to transfer data, and devices coupled to the plurality of network channels. The devices provide or receive data. The system also includes a switch. The switch has a memory for storing compress data, and a plurality of ports coupled to the plurality of network channels. The switch routes data from one port to another port according to a destination port address.

Abstract: A method of detecting sequential data transfer requests, includes determining whether a first data transfer request crosses a boundary address, and, if it does, determining if the first data transfer request may be indicated as combinable with subsequent data transfer requests. The method may also include determining whether a previous data transfer request has been indicated as combinable, and if it has been indicated as combinable, determining that a new data transfer request is addressed adjacent to the previous data transfer request.

Abstract: A controller for a random access memory includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue hat holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.

Abstract: Values are calculated which control the manner in which a display streamer directs the movement of display data. The values are stored in the display streamer.

Abstract: Cells in a non-volatile memory are programmed in parallel using a variable program bandwidth. The variable program bandwidth is an automatic variation in the number of cells pulsed in parallel based upon a predefined electrical current provisioning capability. The variation in programming number may be based upon whether a program pulse represents an initial pulse or a re-pulse. Additionally, or alternatively, the variation in programming number may be based upon a cell level to be programmed by a pulse in a MLC device.

Abstract: Embodiments of the invention provide a compact, seal-less, centrifugal liquid pump with a perimeter magnetic drive that is substantially smaller than a conventional centrifugal liquid pump having magnets attached directly to the impeller shaft. Because rotational force is applied at the perimeter of the impeller, rather than at the shaft, embodiments of the invention have lower torque requirements and rotational speed, increasing the life of the pump bearings. Additionally, embodiments of the invention may suspend the pump bearings by using a redirected flow of liquid coolant, further increasing the bearing life.

Abstract: Embodiments of the invention include a system for driving a slave device of a serial bus when the serial bus is otherwise unused. A bus mastering device, which can be a CPU, controls a data line and a clock line of the serial bus. The bus mastering device sends a command to the slave device over the data line, and then drives the clock line of the serial bus with a clock signal. The slave device accepts the clock signal, and uses it as a clock signal to drive functions of the slave device. Existing serial bus standards may be maintained, or proprietary bus standards can be used.

Abstract: A multihomed network distributes load information associated with different source address prefixes. A host dynamically balances the network load by directing global network traffic according to the load information. Load information may be delivered to the host using existing communication mechanisms, such as the neighbor discovery messages.

Abstract: Plasma etching is controlled utilizing two etchant gases to form a plasma so as to obtain controlled (e.g., uniform) etch rate across a wafer. One etchant gas forms appositive plasma, which is the dominant plasma. The other etchant gas forms a negative plasma, which is the secondary plasma. The ratio of dominant plasma to the secondary plasma can be adjusted such that ion densities are uniform across the wafer, resulting in uniform etch rate over the wafer.

Abstract: A memory device having a wear out counter. The memory device includes at least one block of memory, that block having a metadata section associated with it. A number of bits in the metadata section are used to store the current state of a wear out counter. As the block is accessed, the counter is incremented, allowing a memory controller to level usage and to rectify any problems associated with wear out of that block. A method for incrementing the counter is also included.

Abstract: Circuitry for controlling the oscillation frequency of an oscillator by using a digitally tunable on-chip capacitor bank. The capacitor bank includes a plurality of on-chip capacitors, each of which is independently selectable by a control signal for providing a selectable amount of capacitance to the oscillator to control the oscillator's oscillation frequency.

Abstract: Circuitry for controlling the oscillation frequency of an oscillator by using a digitally tunable on-chip capacitor bank. The capacitor bank includes a plurality of on-chip capacitors, each of which is independently selectable by a control signal for providing a selectable amount of capacitance to the oscillator to control the oscillator's oscillation frequency.

Abstract: A signal propagation system includes a plurality of memory modules that receive a clock signal from a system clock generator. A backplane has a first clock line that propagates a clock signal from the generator to a first memory module of the plurality of memory modules. The backplane may also include a second line that propagates a clock signal between the first and a second memory module of the plurality. The first memory module may include an onboard transmission line that propagates a clock signal between respective first and second clock lines of the backplane.

Abstract: In one embodiment, a digital-signal processor (DSP) is described for multi-level global accumulation. The DSP includes a plurality of absolute difference determinators in a first stage. The absolute difference determinators may include arithmetic logic-units (ALUS) in combination with multiplexers. By using multiple absolute difference determinators, the throughput of the DSP is increased. An existing multiplier may be reconfigured into an adder tree to process the absolute difference results obtained in the first stage. To further increase, throughput, multiple DSPs with multiple absolute difference determinators may be operated in parallel.

Abstract: The method includes detecting and prioritizing one or more interrupt service requests; inserting interrupt servicing instructions responsive to the interrupt service request into an instruction queue mechanism; and processing the instructions within the instruction queue mechanism including the inserted interrupt servicing instructions. The instruction queue mechanism may include an instruction cache and an instruction fetch unit for fetching instructions from the instruction cache, wherein the processing includes decoding the instructions into micro-opcodes and executing the micro-opcodes in one or more out-of-order execution units. The method further includes retiring the executed micro-opcodes including those micro-opcodes representing the inserted interrupt servicing instructions to the instruction cache. Preferably, the criteria for interrupting the core processor include the priority of the interrupts and the capacity of the processor to allocate bandwidth to interrupt servicing.

Abstract: The apparatus involves a hand-held housing with a memory for storing coded audio event data, a mechanism for downloading into the memory coded audio event data and digital-audio electronics for retrieving coded audio event data from memory, converting it to an audio signal and playing it out. In one disclosed embodiment of the invention, the data are stored in accordance with a musical instrument digital interface (MIDI) standard, and may be created on an appropriately equipped personal computer (PC). The capacity of such a hand-held device is far greater than if the data were conventionally digitized or coded. A wirelessly networked system of such music devices in physical proximity is disclosed that enables audio score synthesis and mixing by at least one such device of a synthesized score and an inputted score for outplay to others in a real-time musical jam or music-sharing session.

Abstract: A network processor that has multiple processing elements, each supporting multiple simultaneous program threads with access to shared resources in an interface. Packet data is received from high-speed ports in segments and each segment is assigned to one of the program threads. Each packet may be assigned to a single program thread, two program threads—one for header segment processing and the other for handling payload segment(s)—or a different program thread for segment of data in a packet. Dedicated inputs for ready status and sequence numbers provide assistance needed for receiving the packet data over a high speed port. The dedicated inputs are used to monitor ready flags from the high speed ports on a cycle-by-cycle basis. The sequence numbers are used by the assigned threads to maintain ordering of segments within a packet, as well as to order the writes of the complete packets to transmit queues.

Abstract: An information cell transmission method includes receiving flow control cells at a switch from a collection of multicast virtual circuits and aggregating the flow control cells to form an aggregate flow control cell. A network switch includes first and second port circuitry and control circuitry. The first port circuitry is operative to exchange flow control cells on a collection of multicast virtual circuits coupling the switch to destination nodes. The second port circuitry is operative to exchange flow control cells on another virtual circuit that couples the switch to a source node. The control circuitry is operatively couples the collection of multicast virtual circuits to the source virtual circuit via the first and second port circuitry.

Abstract: Methods and devices for calibrating a driver on a slave device, using a master device driver as a load, are disclosed. A master reference driver is integrated on the same circuit as the master device driver, with both drivers having the same layout and geometry. The master reference driver is calibrated using a selected load impedance that includes the nominal slave device driver impedance and any other impedance elements. The same calibrated driver setting is concurrently applied to both the master driver and the master reference driver, while the slave device drives the master driver. The voltage at the master driver is compared to the voltage at the master reference driver, and the slave device driver impedance is adjusted until those voltages match. The resulting calibration of the slave device driver impedance is largely independent of the actual impedance of the master device driver.

Abstract: An apparatus having a core processor and a plurality of cache memory banks is disclosed. The cache memory banks are connected to the core processor in such a way as to provide substantially simultaneous data accesses for said core processor.