Abstract: Some embodiments of the invention maintain a high degree of overall logic analysis and debug capabilities while simultaneously enabling the reduction of logic analyzer design complexity. Other embodiments of the invention provide a logical analyzer interface (LAI) mode of operation to memory module buffers by adding additional LAI features to the silicon designed to also operate in a normal mode. Other embodiments of the invention are described in the claims.

Abstract: Some embodiments of the invention effectively shield signal traces on a substrate without impacting the signal trace routing on the metal layers of the substrate. Other embodiments of the invention provide improved power delivery without impacting the signal trace routing on the metal layers of the substrate. Other embodiments of the invention are described in the claims.

Abstract: Systems and methods are disclosed for facilitating communication between execution units in a processor. In one embodiment, an integer unit is provided with a set of shadow registers corresponding to each of a plurality of datapath units. Each shadow register is communicatively coupled to a datapath unit, and contains a copy of the contents of the datapath unit's accumulator register. When data is written to a datapath unit's accumulator register, it is also written to a shadow register in the integer unit, where it can be used by the integer unit in further computations.

Abstract: A high resistance region may be used to isolate the body of a first transistor from a body contact.

Abstract: Systems and methods are disclosed for facilitating dynamic resource allocation in a limited memory environment. In one embodiment, a master code image is created that includes one or more alternative implementations of an interface. When it is determined that a particular implementation of the interface is desired, the alternative implementations are removed from the master code image, and the resulting code image is compiled. The program is then used to process network traffic. If a condition is subsequently detected that could be handled more efficiently by one of the alternative interface implementations, the process can be repeated, and the resulting program used to process further network traffic.

Abstract: A single-version data cache processes speculative stores using one or more checkpoints.

Abstract: A processor enabled with checkpoints may be used to recover registers using counter entry and release.

Abstract: Checkpoints may be used to recover from branch mispredictions using scalable rename map table recovery.

Abstract: Systems and methods for scalable packet buffer descriptor management in ATM-Ethernet bridge gateways are disclosed. An ATM-Ethernet processor interfacing between an ATM processor and an Ethernet network processor generally includes a packet buffer pointer ring containing ATM processor packet buffer pointers for managing traffic from the Ethernet network processor to the ATM processor, and a packet descriptor ring and a data buffer for managing traffic from the ATM processor to the Ethernet network processor. The packet descriptor ring contains packet descriptors each including an ATM-Ethernet packet buffer memory address in the data buffer. The ATM processor may be in communication with a SONET framer while the Ethernet network processor may be in communication with an Ethernet MAC.

Abstract: Systems and methods are disclosed for implementing software FIFOs on network processing engines (NPEs). The logic needed to support these software FIFOs is believed to be less than that needed to support additional hardware FIFOs, especially as the number of additional FIFOs is increased. Thus, the systems and methods enable NPEs to utilize more FIFOs at less cost. The counting semaphores that are used in the implementation of the software FIFOs can also, or alternatively, be used to provide NPEs with additional resource-locking and signaling functionality.

Abstract: Methods and devices for wire-speed packet statistics collection in a network processor are disclosed. A control-plane process maintains a dynamic packet rule set, each rule specifying a packet offset, a data pattern to be found at that offset, and an action to be taken if that data pattern is found. One or more packet processing engines process the packet rule set for incoming packets and take actions such as updating counters in a counter table when a rule evaluates true. The control-plane process can access the counter table to monitor which rules are triggered by packet traffic with what frequency.

Abstract: The response time from a client on a network is measured and a destination address is selected based on the measured response time. The client requests an address from the network. The network may be a local network or a wide area network such as the Internet. The response time of the client is measured to determine the optimum speed at which the client may operate. The measured response time is communicated to the server, where a destination address is selected based on the requested address and the measured response time. The client may then be connected to the destination address.

Abstract: A thinned semiconductor die is coupled to an integrated heat spreader with thermal interface material to form a semiconductor package. The method for forming the package comprises forming a metallization layer on a backside of a thinned semiconductor die. A thermal interface portion, including a solder layer including a fluxlessly-capable solder such as AuSn, is formed on a topside of the integrated heat spreader. The metallization layer and the solder layer are then forced together under load and heat without flux to bond the semiconductor die to the integrated heat spreader.

Abstract: A protection circuit that permits the use of thin oxide transistor devices. In one embodiment, the circuit is used to protect internal nodes of a flash EEPROM chip from a power pad voltage. A thin oxide device can be used to directly couple the power pad to an internal node of the flash chip. Optionally, thin oxide devices can also be used to set the steady state internal node voltage and a current source can be coupled to the node to bleed sub-threshold current. In yet another embodiment, a pull down circuit is coupled to the node to pull the node immediately down to a desired steady state voltage when the EEPROM algorithm is completed.

Abstract: A nonvolatile memory module. The module includes a nonvolatile memory array and a connector allowing the array to make connection with a host system. A memory controller operates to either create an image of a nonvolatile intermediate memory in response to an imaging request or populate a nonvolatile intermediate memory in response to an installation request.

Abstract: A current summing FIR filter can be implemented with multiple differential input stages and variable tail currents. The variable tail currents can be used to appropriately weight the present and previous digital input signals. The weighted outputs of the differential transistor pairs can be summed to provide a filtered output signal. The tail currents can be advantageously varied with variable current sources or by adjustment of the relative widths of the differential transistor pairs. In other embodiments, additional differential pairs can be added to adjust for systematic offset voltages caused by process-induced variations in the structure of circuit devices or to induce a desired offset.

Abstract: In an embodiment, a pipelined digital signal processor (DSP) may generate a valid bit in an alignment stage. The valid bit may be qualified in a decode stage in response to receiving a stall signal and/or a kill signal. The valid bit output from the decode stage may be stored in a latch in an address calculation (AC) stage. The valid bit may be held in the latch by a latch enable circuit in response to receiving a stall signal. The valid bit output from the latch may be qualified in the AC stage. The circuit in the AC stage including the latch, the latch enable circuit, and a valid bit qualifier may be repeated in downstream pipeline stages, for example, the execution stages.

Abstract: An apparatus and method for memory allocation with digital processing systems comprises a first memory bank, a hardware register, and a processing circuit configured to write the contents of the hardware register to a memory address in the first memory bank, and to write the memory address to the hardware register. In an embodiment, a pointer list containing memory pointer values may be maintained in the first memory bank. The first memory bank may contain associated data buffers, and a second memory bank may contain corresponding data buffers such that an associated data buffer and a corresponding data buffer may be located from a single memory pointer value.

Abstract: A packet of encoded data is received and decoded using a look-up table that stores information approximating output of an algorithmic decoding process.

Abstract: Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The buffers allow the memory interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the buffers. The second sub-interface is between the buffers and the memory modules. The method also includes interleaving output of the buffers, and configuring the buffers to properly latch the data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.